SNVS673E April   2010  – September 2014 LP8551

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Default Values
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Boost Converter Electrical Characteristics
    7. 7.7  LED Driver Electrical Characteristics
    8. 7.8  PWM Interface Characteristics
    9. 7.9  Undervoltage Protection
    10. 7.10 Logic Interface Characteristics
    11. 7.11 I2C Serial Bus Timing Parameters (SDA, SCLK)
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Generation
      2. 8.3.2 Brightness Control Methods
        1. 8.3.2.1  PWM Input Duty Cycle
        2. 8.3.2.2  Brightness Register Control
        3. 8.3.2.3  PWM Direct Control
        4. 8.3.2.4  PWM Calculation Data Flow
        5. 8.3.2.5  PWM Detector
        6. 8.3.2.6  Brightness Control
        7. 8.3.2.7  Resolution Selector
        8. 8.3.2.8  Sloper
        9. 8.3.2.9  PWM Comparator
        10. 8.3.2.10 Current Setting
        11. 8.3.2.11 PWM Frequency Setting
        12. 8.3.2.12 Phase Shift PWM (PSPWM) Scheme
        13. 8.3.2.13 Slope
        14. 8.3.2.14 Driver Headroom Control
      3. 8.3.3 Boost Converter
        1. 8.3.3.1 Operation
        2. 8.3.3.2 Protection
        3. 8.3.3.3 Manual Output Voltage Control
        4. 8.3.3.4 Adaptive Boost Control
      4. 8.3.4 Fault Detection
        1. 8.3.4.1 LED Fault Detection
        2. 8.3.4.2 Undervoltage Detection
        3. 8.3.4.3 Overcurrent Protection
        4. 8.3.4.4 Device Thermal Regulation
        5. 8.3.4.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Bus Interface
        1. 8.5.1.1 Interface Bus Overview
        2. 8.5.1.2 Data Transactions
        3. 8.5.1.3 Acknowledge Cycle
        4. 8.5.1.4 “Acknowledge After Every Byte” Rule
        5. 8.5.1.5 Addressing Transfer Formats
        6. 8.5.1.6 Control Register Write Cycle
        7. 8.5.1.7 Control Register Read Cycle
        8. 8.5.1.8 Register Read and Write Detail
      2. 8.5.2 EEPROM
    6. 8.6 Register Map
      1. 8.6.1 Register Bit Explanations
        1. 8.6.1.1 Brightness Control
        2. 8.6.1.2 Device Control
        3. 8.6.1.3 Fault
        4. 8.6.1.4 Identification
        5. 8.6.1.5 Direct Control
        6. 8.6.1.6 Temp MSB
        7. 8.6.1.7 Temp LSB
        8. 8.6.1.8 EEPROM Control
      2. 8.6.2 EEPROM Bit Explanations
        1. 8.6.2.1 EEPROM Register Map
        2. 8.6.2.2 EEPROM Address 0
        3. 8.6.2.3 EEPROM Address 1
        4. 8.6.2.4 EEPROM Address 2
        5. 8.6.2.5 EEPROM Address 3
        6. 8.6.2.6 EEPROM Address 4
        7. 8.6.2.7 EEPROM Address 5
        8. 8.6.2.8 EEPROM Address 7
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Using Internal LDO
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Recommended External Components
            1. 9.2.1.2.1.1 Inductor Selection
            2. 9.2.1.2.1.2 Output Capacitor
            3. 9.2.1.2.1.3 LDO Capacitor
            4. 9.2.1.2.1.4 Output Diode
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application with Low-Input Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 24 V
VLDO –0.3 6
Voltage on logic pins (PWM, EN, SCLK, SDA) –0.3 6
Voltage on logic pin (FAULT) –0.3 to VDDIO + 0.3
Voltage on analog pins (VDDIO, ISET, FSET) –0.3 6
V (OUT1...OUT4, SW, FB) –0.3 44
Continuous power dissipation(2) Internally limited
Junction temperature (TJ-MAX) 125 °C
Maximum lead temperature (soldering)(3)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.).
(3) For detailed soldering specifications and information, please refer to TI's AN-1112 (SNVA009): DSBGA Wafer Level Chip Scale Package.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2000 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –1000 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(1)(2)

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage (VIN) (Figure 22) 5.5 22 V
Input voltage (VIN + VLDO)(Figure 25) 4.5 5.5
VDDIO 1.65 5
V(OUT1 to OUT4, SW, FB) 0 40
Junction temperature (TJ) –30 125 °C
Ambient temperature (TA)(3) –30 85
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

7.4 Thermal Information

THERMAL METRIC(1) DSBGA (YZR) UNIT
25 PINS
RθJA Junction-to-ambient thermal resistance (2) 40 to 73 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.5 Electrical Characteristics(1)(2)

Limits are for TA = 25°C and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ(3)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIN Standby supply current Internal LDO disabled
EN=L and PWM=L		 1(4) μA
Normal mode supply current LDO enabled, boost enabled, no current going through LED outputs
5-MHz PLL Clock		 3 mA
10-MHz PLL Clock 3.7
20-MHz PLL Clock 4.7
40-MHz PLL Clock 6.7
fOSC Internal oscillator frequency accuracy –4%
–7%(4)		 4%
7%(4)
VLDO Internal LDO voltage 4.5(4) 5 5.5(4) V
ILDO Internal LDO external loading 5 mA
(1) All voltages are with respect to the potential at the GND pins.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most likely norm.
(3) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.
(4) Limits apply over the full operating ambient temperature range (–30°C ≤ TA ≤ 85°C).

7.6 Boost Converter Electrical Characteristics

Limits are for TA = 25°C and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ(1)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RDSON Switch ON resistance ISW = 0.5 A 0.12 Ω
VMAX Boost maximum output voltage 40 V
ILOAD Maximum continuous load current 9 V ≤ VBATT, VOUT = 35 V 450 mA
6 V ≤ VBATT, VOUT = 35 V 300
3 V ≤ VBATT, VOUT = 25 V 180
VOUT/VIN Conversion ratio fSW = 1.25 MHz 10
fSW Switching frequency BOOST_FREQ = 00
BOOST_FREQ = 01
BOOST_FREQ = 10
BOOST_FREQ = 11		 156
312
625
1250		 kHz
VOV Overvoltage protection voltage VBOOST + 1.6V V
tPULSE Switch pulse minimum width no load 50 ns
tSTARTUP Start-up time See (2) 6 ms
IMAX SW pin current limit IMAX_SEL = 0
IMAX_SEL = 1		 1.4
2.5		 A
(1) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(2) Start-up time is measured from the moment boost is activated until the VOUT crosses 90% of its target value.

7.7 LED Driver Electrical Characteristics

Limits are for TA = 25°C and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ(2)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILEAKAGE Leakage current Outputs OUT1...OUT4, VOUT = 40 V 0.1 1 μA
IMAX Maximum source current OUT1...OUT4 EN_I_RES = 0, CURRENT[7:0] = FFh 30 mA
EN_I_RES = 1, CURRENT[7:0] = FFh 50
IOUT Output current accuracy(3) Output current set to 23 mA, EN_I_RES = 1 –3%
–4%(1)		 3%
4%(1)
IMATCH Matching(3) Output current set to 23 mA, EN_I_RES = 1 0.5%
PWMRES PWM output resolution(5) fLED = 5 kHz, fPLL = 5 MHz 10 bits
fLED = 10 kHz, fPLL = 5 MHz 9
fLED = 20 kHz, fPLL = 5 MHz 8
fLED = 5 kHz, fPLL = 40 MHz 13
fLED = 10 kHz, fPLL = 40 MHz 12
fLED = 20 kHz, fPLL = 40 MHz 11
fLED LED switching frequency(5) PWM_FREQ[4:0] = 00000b
PLL clock 5 MHz		 600 Hz
PWM_FREQ[4:0] = 11111b
PLL clock 5 MHz		 19.2k
VSAT Saturation voltage(4) Output current set to 20 mA 105 220(1) mV
Output current set to 30 mA 160 290(1)
(1) Limits apply over the full operating ambient temperature range (–30°C ≤ TA ≤ 85°C).
(2) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.
(3) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN/AVG). The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use.
(4) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.
(5) PWM output resolution and frequency depend on the PLL settings. Please see sectionPWM Frequency Setting for full description.

7.8 PWM Interface Characteristics

Limits are for TA = 25°C and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ(1)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ƒPWM PWM frequency range 0.1 25 kHz
tMIN_ON Minimum pulse ON time 1 μs
tMIN_OFF Minimum pulse OFF time 1
tSTARTUP Turnon delay from standby to backlight on PWM input active, EN pin rise from low to high 6 ms
TSTBY Turnoff Delay PWM input low time for turn off, slope disabled 50 ms
PWMRES PWM Input Resolution ƒIN < 9 kHz
ƒIN < 4.5 kHz
ƒIN < 2.2 kHz
ƒIN < 1.1 kHz		 10
11
12
13		 bits
(1) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

7.9 Undervoltage Protection

Limits are for TA = 25°C and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ(1)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO VIN UVLO Threshold Voltage UVLO[1:0] = 00 Disabled V
UVLO[1:0] = 01, falling 2.55 2.70 2.94
UVLO[1:0] = 01, rising 2.62 2.76 3.00
UVLO[1:0] = 10, falling 5.11 5.40 5.68
UVLO[1:0] = 10, rising 5.38 5.70 5.98
UVLO[1:0] = 11, falling 7.75 8.10 8.45
UVLO[1:0] = 11, rising 8.36 8.73 9.20
(1) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

7.10 Logic Interface Characteristics

Limits apply over the full operating ambient temperature range (–30°C ≤ TA ≤ 85°C), and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ(2)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUT EN
VIL Input low level 0.4 V
VIH Input high level 1.2 V
II Input current –1 1 μA
LOGIC INPUT PWM
VIL Input low level 0.4 V
VIH Input high level 2.2 V
II Input current –1 1 μA
LOGIC INPUTS SCL, SDA
VIL Input low level 0.2xVDDIO V
VIH Input high level 0.8xVDDIO V
II Input current μA
LOGIC OUTPUTS SDA, FAULT
VOL Output low level IOUT = 3 mA (pullup current) 0.3(1) 0.5 V
IL Output leakage current VOUT = 2.8 V –1 1 μA
(1) Limits are TA = 25 °C.
(2) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

7.11 I2C Serial Bus Timing Parameters (SDA, SCLK)(1)

SYMBOL PARAMETER MIN MAX UNIT
ƒSCLK Clock frequency 400 kHz
1 Hold time (repeated) START condition 0.6 μs
2 Clock low time 1.3 μs
3 Clock high time 600 ns
4 Setup time for a repeated START condition 600 ns
5 Data hold time 50 ns
6 Data setup time 100 ns
7 Rise time of SDA and SCL 20+0.1Cb 300 ns
8 Fall time of SDA and SCL 15+0.1Cb 300 ns
9 Setup time for STOP condition 600 ns
10 Bus free time between a STOP and a START condition 1.3 μs
Cb Capacitive load parameter for each bus line
Load of 1 pF corresponds to 1 ns.		 10 200 ns
(1) Specified by design. VDDIO = 1.65 V to 5.5 V.
30121298.pngFigure 1. I2C Timing Parameters

7.12 Typical Characteristics

Unless otherwise specified: VBATT= 12 V, CVLDO= 1 μF, L1 = 33 μH, CIN= 10 μF, COUT= 10 μF.
30121292.png
ƒLED= 9.6 kHz
Figure 2. LED Drive Efficiency
30121290.png
Figure 4. Boost Converter Efficiency
301212100.gif
Figure 6. ILED vs. RISET
30121293.png
ƒLED= 9.6 kHz L1 = 15 μH
Figure 3. LED Drive Efficiency
30121209.gif
Figure 5. Battery Current
30121284.png
Figure 7. Boost Line Transient Response