JAJSG64C March   2015  – August 2018 LP8758-B0

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概略回路図
    1.     効率と出力電流との関係(VIN = 3.7V)
  5. 5 改訂履歴
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameter
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Buck Information
        1. 8.1.1.1 Operating Modes
        2. 8.1.1.2 Features
        3. 8.1.1.3 Programmability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multi-Phase DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multi-Phase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Power-Up
      3. 8.3.3 Regulator Control
        1. 8.3.3.1 Enabling and Disabling Regulator
        2. 8.3.3.2 Changing Output Voltage
      4. 8.3.4 Device Reset Scenarios
      5. 8.3.5 Diagnosis and Protection Features
        1. 8.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 8.3.5.1.1 Output Current Limit
          2. 8.3.5.1.2 Thermal Warning
        2. 8.3.5.2 Protection (Regulator Disable)
          1. 8.3.5.2.1 Short-Circuit and Overload Protection
          2. 8.3.5.2.2 Thermal Shutdown
        3. 8.3.5.3 Fault (Power Down)
          1. 8.3.5.3.1 Undervoltage Lockout
      6. 8.3.6 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  DEV_REV
        2. 8.6.1.2  OTP_REV
        3. 8.6.1.3  BUCK0_CTRL1
        4. 8.6.1.4  BUCK0_CTRL2
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL2
        7. 8.6.1.7  BUCK3_CTRL2
        8. 8.6.1.8  BUCK0_VOUT
        9. 8.6.1.9  BUCK0_FLOOR_VOUT
        10. 8.6.1.10 BUCK0_DELAY
        11. 8.6.1.11 RESET
        12. 8.6.1.12 CONFIG
        13. 8.6.1.13 INT_TOP
        14. 8.6.1.14 INT_BUCK_0_1
        15. 8.6.1.15 INT_BUCK_2_3
        16. 8.6.1.16 TOP_STAT
        17. 8.6.1.17 BUCK_0_1_STAT
        18. 8.6.1.18 BUCK_2_3_STAT
        19. 8.6.1.19 TOP_MASK
        20. 8.6.1.20 BUCK_0_1_MASK
        21. 8.6.1.21 BUCK_2_3_MASK
        22. 8.6.1.22 SEL_I_LOAD
        23. 8.6.1.23 I_LOAD_2
        24. 8.6.1.24 I_LOAD_1
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Input Capacitor Selection
          3. 9.2.2.1.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise noted.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN Input filtering capacitance Connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT Output filtering capacitance, local Capacitance per phase 10 22 µF
COUT-TOTAL Output capacitance, total (local and remote) Total output capacitance, 4-phase configuration 40 200 µF
ESRC Input and output capacitor ESR [1-10] MHz 2 10 mΩ
L Inductor Inductance of the inductor 0.33 or 0.47 µH
–30% 30%
DCRL Inductor DCR TOKO, DFE252010F-R33M 16 mΩ
BUCK REGULATOR
VIN Input voltage range Voltage between VIN_Bx and ground pins. VANA must be connected to the same supply as VIN_Bx. 2.5 3.7 5.5 V
VOUT Output voltage Programmable voltage range 0.5 1 3.36 V
Step size, 0.5 V ≤ VOUT < 0.73 V 10 mV
Step size, 0.73 V ≤ VOUT < 1.4 V 5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20
IOUT Output current Output current, 4-phase configuration 12(3) A
Output current, 4-phase configuration, VIN > 3 V, VOUT < 2 V 16(3)
Dropout voltage VIN – VOUT 0.7 V
DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Forced PWM mode, 0.8 V ≤ VOUT ≤ 1.2 V, 2.5 V ≤ VIN ≤ 4.5 V, TJ = 25°C, 0 ≤ IOUT ≤ IOUT(max) -1% 1.5%
PFM mode, the average output voltage level is increased by max. 20 mV min (–2%,
–15 mV)		 max ( 2%, 15 mV) 20 mV
Ripple, 4-phase configuration PWM mode, L = 0.33 µH 10 mVp-p
PFM mode, L = 0.33 µH 10
DCLNR DC line regulation IOUT = IOUT(max) ±0.05 %/V
DCLDR DC load regulation in PWM mode IOUT from 0 to IOUT(max) 0.3%
TLDSR Undershoot for transient load step response, 4-phase configuration IOUT = 1 A to 8 A, TR = 400 ns, PWM mode, COUT = 100 µF, L = 0.33 µH -45 mV
2.5 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V, IOUT = 0.1 A to 4.1 A, TR = 100 ns, AUTO mode, COUT = 100 µF, L = 0.33 µH –35 mV
3 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V, IOUT from 1 A to 12 A, TR = 1000 ns, COUT = 100 µF, L = 0.33 µH –45 mV
Overshoot for transient load step response, 4-phase configuration IOUT = 8 A to 1 A, TF = 400 ns, PWM mode, COUT = 100 µF, L = 0.33 µH 45 mV
2.5 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V, IOUT = 4.1 A to 0.1 A, TF = 100 ns, AUTO mode, COUT = 100 µF, L = 0.33 µH 25 mV
3 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V, IOUT from 12 A to 1 A, TF = 1000 ns, COUT = 100 µF, L = 0.33 µH 50 mV
TLNSR Transient line response VIN stepping 2.5 V ↔ 3 V, TR = TF = 10 µs, IOUT = IOUT(max) ±20 mV
ILIM FWD Forward current limit (peak for every switching cycle) Programmable range 1.5 5 A
Step size 0.5
Accuracy, 3 V ≤ VIN ≤ 5.5 V, ILIM = 5 A –5% 7.5% 20%
Accuracy, 2.5 V ≤ VIN < 3 V, ILIM = 5 A –20% 7.5% 20%
ILIM NEG Negative current limit 1.6 2 2.4 A
RDS(ON) HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 40 90 mΩ
RDS(ON) LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 33 50 mΩ
Current balancing Current mismatch between phases, IOUT > 1000 mA / phase, 0.8 V ≤ VOUT ≤ 1.2 V 10%
Overshoot during start-up VOUT = 1 V, Slew rate = 10 mV/µs 50 mV
IPFM-PWM PFM-to-PWM transition - current threshold(4) 600 mA
IPWM-PFM PWM-to-PFM transition - current threshold(4) 240 mA
IADD Phase-adding level From 1-phase to 2-phase 1000 mA
From 2-phase to 3-phase 2000
From 3-phase to 4-phase 3000
ISHED Phase-shedding level From 2-phase to 1-phase 750 mA
From 3-phase to 2-phase 1500
From 4-phase to 3-phase 2300
Output pulldown resistance Regulator disabled 150 250 350 Ω
Powergood threshold for interrupt BUCKx_INT(BUCKx_SC_INT), difference from final voltage Rising ramp voltage, enable or voltage change –23 –17 –10 mV
Falling ramp, voltage change 10 17 23
Powergood threshold for status signal BUCKx_STAT(BUCKx_PG_STAT) During operation, status signal is forced to '0' during voltage change –23 –17 –10 mV
PROTECTION FEATURES
Thermal warning Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 0 125 °C
Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 1 105
Hysteresis 15
Thermal shutdown Temperature rising 150 °C
Hysteresis 15
VANAUVLO VANA undervoltage lockout Voltage falling 2.3 2.4 2.5 V
Hysteresis 50 mV
LOAD CURRENT MEASUREMENT
Current measurement range Maximum code 20.46 A
Resolution LSB 20 mA
Measurement accuracy IOUT ≥ 2 A <10%
CURRENT CONSUMPTION
Shutdown current consumption V(NRST) = 0 V 1 µA
Standby current consumption, regulator disabled V(NRST) = 1.8 V 6 µA
Active current consumption during PFM operation V(NRST) = 1.8 V, IOUT = 0 mA, not switching 71 µA
Active current consumption during PWM operation V(NRST) = 1.8 V, IOUT = 0 mA 18 mA
DIGITAL INPUT SIGNALS NRST, ENx, SCL, SDA
VIL Input low level 0.4 V
VIH Input high level 1.2 V
VHYS Hysteresis of Schmitt trigger inputs (SCL, SDA) 10 80 160 mV
ENx pulldown resistance ENx_PD = 1 500 kΩ
NRST pulldown resistance Always present 800 1200 1700 kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL Output low level ISOURCE = 2 mA 0.4 V
RP External pullup resistor for nINT To VIO Supply 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs over pin voltage range −1 1 µA
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.
(3) The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature. The maximum average current/pin over lifetime is described in Absolute Maximum Ratings.
(4) The final PFM-to-PWM and PWM-to-PFM transition current varies slightly and is dependant on the output voltage, input voltage, and the magnitude of inductor's ripple current.