JAJSSO2 December   2023 MCF8315C

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
        6. 6.3.3.6 Buck Under Voltage Protection
        7. 6.3.3.7 Buck Over Current Protection
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog Mode Motor Control
        2. 6.3.8.2 PWM Mode Motor Control
        3. 6.3.8.3 I2C based Motor Control
        4. 6.3.8.4 Frequency Mode Motor Control
        5. 6.3.8.5 Speed Profiles
          1. 6.3.8.5.1 Linear Reference Profiles
          2. 6.3.8.5.2 Staircase Reference Profiles
          3. 6.3.8.5.3 Forward-Reverse Reference Profiles
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
      11. 6.3.11 Motor Start-up
        1. 6.3.11.1 Align
        2. 6.3.11.2 Double Align
        3. 6.3.11.3 Initial Position Detection (IPD)
          1. 6.3.11.3.1 IPD Operation
          2. 6.3.11.3.2 IPD Release Mode
          3. 6.3.11.3.3 IPD Advance Angle
        4. 6.3.11.4 Slow First Cycle Start-up
        5. 6.3.11.5 Open loop
        6. 6.3.11.6 Transition from Open to Closed Loop
      12. 6.3.12 Closed Loop Operation
        1. 6.3.12.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.12.2 Speed PI Control
        3. 6.3.12.3 Current PI Control
        4. 6.3.12.4 Torque Mode
        5. 6.3.12.5 Overmodulation
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Modulation Schemes
      19. 6.3.19 Dead Time Compensation
      20. 6.3.20 Motor Stop Options
        1. 6.3.20.1 Coast (Hi-Z) Mode
        2. 6.3.20.2 Low-Side Braking
        3. 6.3.20.3 Active Spin-Down
      21. 6.3.21 FG Configuration
        1. 6.3.21.1 FG Output Frequency
        2. 6.3.21.2 FG during open loop
        3. 6.3.21.3 FG during idle and fault
      22. 6.3.22 DC Bus Current Limit
      23. 6.3.23 Protections
        1. 6.3.23.1  VM Supply Undervoltage Lockout
        2. 6.3.23.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.23.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.23.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.23.5  Overvoltage Protection (OVP)
        6. 6.3.23.6  Overcurrent Protection (OCP)
          1. 6.3.23.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.23.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.23.7  Buck Overcurrent Protection
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 6.3.23.9  Motor Lock (MTR_LCK)
          1. 6.3.23.9.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.23.9.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.23.9.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.23.9.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        10. 6.3.23.10 Motor Lock Detection
          1. 6.3.23.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.23.11 Minimum VM (undervoltage) Protection
        12. 6.3.23.12 Maximum VM (overvoltage) Protection
        13. 6.3.23.13 MPET Faults
        14. 6.3.23.14 IPD Faults
        15. 6.3.23.15 Thermal Warning (OTW)
        16. 6.3.23.16 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC output (only in RRY package)
      3. 6.5.3 Oscillator Source
        1. 6.5.3.1 External Clock Source
      4. 6.5.4 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Internal_Algorithm_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Device_Control Registers
      4. 6.8.4 Algorithm_Control Registers
      5. 6.8.5 Algorithm_Variables Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 MPET
        3. 7.2.1.3 Dead time compensation
        4. 7.2.1.4 Auto handoff
        5. 7.2.1.5 Anti voltage surge (AVS)
        6. 7.2.1.6 Real time variable tracking using DACOUT
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Thermal Considerations
      1. 9.2.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 サポート・リソース
    2. 10.2 Trademarks
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7.3 Hardware_Configuration Registers

Table 6-34 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 6-34 should be considered as reserved locations and the register contents should not be modified.

Table 6-34 HARDWARE_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A4hPIN_CONFIGHardware Pin ConfigurationSection 6.7.3.1
A6hDEVICE_CONFIG1Device configuration1Section 6.7.3.2
A8hDEVICE_CONFIG2Device configuration2Section 6.7.3.3
AAhPERI_CONFIG1Peripheral Configuration1Section 6.7.3.4
AChGD_CONFIG1Gate Driver Configuration1Section 6.7.3.5
AEhGD_CONFIG2Gate Driver Configuration2Section 6.7.3.6

Complex bit access types are encoded to fit into small table cells. Table 6-35 shows the codes that are used for access types in this section.

Table 6-35 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

6.7.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Figure 6-73 and described in Table 6-36.

Return to the Summary Table.

Register to configure hardware pins

Figure 6-73 PIN_CONFIG Register
3130292827262524
RESERVEDRESERVEDVDC_FILT_DISRESERVED
R-0hR-0hR/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDFG_IDLE_CONFIGFG_FAULT_CONFIG
R-0hR-0hR/W-0hR/W-0h
76543210
FG_FAULT_CONFIGALARM_PIN_ENRESERVEDRESERVEDBRAKE_INPUTSPEED_MODE
R/W-0hR/W-0hR-0hR-0hR/W-0hR/W-0h
Table 6-36 PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h Reserved
30-28RESERVEDR0h Reserved
27VDC_FILT_DISR/W0h Vdc filter disable
0h = Enable
1h = Disable
26-13RESERVEDR0h Reserved
12-11RESERVEDR0h Reserved
10-9FG_IDLE_CONFIGR/W0h FG configuration during motor stopped/idle state
0h = FG continues and end state depends on FG_CONFIG and last state before motor stops
1h = FG is pulled High
2h = FG is pulled Low
3h = FG is pulled High
8-7FG_FAULT_CONFIGR/W0h FG configuration during fault state
0h = Use last FG signal when motor is driving
1h = FG is pulled High
2h = FG is pulled Low
6ALARM_PIN_ENR/W0h Alarm pin enable
0h = Disable
1h = Enable
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3-2BRAKE_INPUTR/W0h Brake pin override
0h = Hardware pin (BRAKE)
1h = Override pin and apply low-side brake
2h = Override pin and do not brake
3h = Hardware pin (BRAKE)
1-0SPEED_MODER/W0h Configure input reference mode from SPEED pin
0h = Controlled by amplitude of SPEED pin (analog mode)
1h = Controlled by duty cycle of SPEED pin (PWM mode)
2h = Controlled by DIGITAL_SPEED_CTRL register (I2C mode)
3h = Controlled by frequency of SPEED pin (freq. mode)

6.7.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 0XXXXXX0h]

DEVICE_CONFIG1 is shown in Figure 6-74 and described in Table 6-37.

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Register to configure device

Figure 6-74 DEVICE_CONFIG1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDDAC_ENABLEI2C_TARGET_ADDR
R-0hR-0hR-0hR/W-0hR/W-X
2322212019181716
I2C_TARGET_ADDRRESERVED
R/W-XR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSLEW_RATE_I2C_PINSPULLUP_ENABLEBUS_VOLT
R-0hR/W-0hR/W-0hR/W-0h
Table 6-37 DEVICE_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h Reserved
30RESERVEDR0h Reserved
29-28RESERVEDR0h Reserved
27DAC_ENABLER/W0h DAC enable
0h = DACOUT disabled
1h = DACOUT enabled
26-20I2C_TARGET_ADDRR/WX I2C target address
19-5RESERVEDR0h Reserved
4-3SLEW_RATE_I2C_PINSR/W0h Slew rate control for I2C pins
0h = 4.8 mA
1h = 3.9 mA
2h = 1.86 mA
3h = 30.8 mA
2PULLUP_ENABLER/W0h Internal pull-up enable for nFAULT and FG pins
0h = Disable
1h = Enable
1-0BUS_VOLTR/W0h Maximum DC bus voltage configuration
0h = 15 V
1h = 30 V
2h = 60 V
3h = Reserved

6.7.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Figure 6-75 and described in Table 6-38.

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Register to configure device

Figure 6-75 DEVICE_CONFIG2 Register
3130292827262524
RESERVEDINPUT_MAXIMUM_FREQ
R-0hR/W-0h
2322212019181716
INPUT_MAXIMUM_FREQ
R/W-0h
15141312111098
SLEEP_ENTRY_TIMEDYNAMIC_CSA_GAIN_ENDYNAMIC_VOLTAGE_GAIN_ENDEV_MODECLK_SELEXT_CLK_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EXT_CLK_CONFIGEXT_WDT_ENEXT_WDT_CONFIGEXT_WDT_INPUT_MODEEXT_WDT_FAULT_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 6-38 DEVICE_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h Reserved
30-16INPUT_MAXIMUM_FREQR/W0h Input frequency on speed pin for input reference mode as "controlled by frequency of SPEED pin" that corresponds to 100% duty cycle. Duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14SLEEP_ENTRY_TIMER/W0h Device enters sleep mode when SPEED input is held continuously below threshold for SLEEP_ENTRY_TIME
0h = Sleep Entry when SPEED pin remains low for 50 µs
1h = Sleep Entry when SPEED pin remains low for 200 µs
2h = Sleep Entry when SPEED pin remains low for 20 ms
3h = Sleep Entry when SPEED pin remains low for 200 ms
13DYNAMIC_CSA_GAIN_ENR/W0h Adjust CSA gain automatically for optimal current resolution at all current levels
0h = Disable
1h = Enable
12DYNAMIC_VOLTAGE_GAIN_ENR/W0h Adjust voltage gain automatically for optimal voltage resolution at all voltage levels
0h = Disable
1h = Enable
11DEV_MODER/W0h Device mode select
0h = Standby Mode
1h = Sleep Mode
10-9CLK_SELR/W0h Clock source
0h = Internal oscillator
1h = Reserved
2h = Reserved
3h = External clock input
8EXT_CLK_ENR/W0h Enable external clock mode
0h = Disable
1h = Enable
7-5EXT_CLK_CONFIGR/W0h External Clock Configuration
0h = 8 kHz
1h = 16 kHz
2h = 32 kHz
3h = 64 kHz
4h = 128 kHz
5h = 256 kHz
6h = 512 kHz
7h = 1024 kHz
4EXT_WDT_ENR/W0h Enable external watchdog
0h = Disable
1h = Enable
3-2EXT_WDT_CONFIGR/W0h Time between watchdog tickles (GPIO/I2C)
0h = 100ms/1s
1h = 200ms/2s
2h = 500ms/3s
3h = 1000ms/10s
1EXT_WDT_INPUT_MODER/W0h External watchdog input source
0h = Watchdog tickle over I2C
1h = Watchdog tickle over GPIO
0EXT_WDT_FAULT_MODER/W0h External watchdog fault mode
0h = Report only
1h = Latch with MOSFETs in Hi-Z

6.7.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 40000000h]

PERI_CONFIG1 is shown in Figure 6-76 and described in Table 6-39.

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Register to peripheral1

Figure 6-76 PERI_CONFIG1 Register
3130292827262524
RESERVEDSPREAD_SPECTRUM_MODULATION_DISRESERVEDBUS_CURRENT_LIMIT
R-0hR/W-1hR-0hR/W-0h
2322212019181716
BUS_CURRENT_LIMITBUS_CURRENT_LIMIT_ENABLEDIR_INPUTDIR_CHANGE_MODERESERVEDACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYACTIVE_BRAKE_MOD_INDEX_LIMITSPEED_RANGE_SELRESERVED
R/W-0hR/W-0hR/W-0hR-0h
76543210
RESERVED
R-0h
Table 6-39 PERI_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h Reserved
30SPREAD_SPECTRUM_MODULATION_DISR/W1h Spread spectrum modulation disable
0h = SSM is enabled
1h = SSM is disabled
29-26RESERVEDR0h Reserved
25-22BUS_CURRENT_LIMITR/W0h Bus current limit
0h = 0.078125 A
1h = 0.15625 A
2h = 0.3125 A
3h = 0.625 A
4h = 0.9375 A
5h = 1.25 A
6h = 1.5625 A
7h = 1.875 A
8h = 2.1875 A
9h = 2.5 A
Ah = 2.8125 A
Bh = 3.125 A
Ch = 3.4375 A
Dh = 3.75 A
Eh = 4.375 A
Fh = 5.0 A
21BUS_CURRENT_LIMIT_ENABLER/W0h Bus current limit enable
0h = Disable
1h = Enable
20-19DIR_INPUTR/W0h DIR pin override
0h = Hardware pin (DIR)
1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC
2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB
3h = Hardware pin (DIR)
18DIR_CHANGE_MODER/W0h Response to change of DIR pin status
0h = Follow motor stop options and ISD routine on detecting DIR change
1h = Change the direction through reverse drive while continuously driving the motor
17RESERVEDR0h Reserved
16-13ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYR/W0h Difference between final speed and present speed below which active braking will be applied
0h = reserved
1h = 5%
2h = 10%
3h = 15%
4h = 20%
5h = 25%
6h = 30%
7h = 35%
8h = 40%
9h = 45%
Ah = 50%
Bh = 60%
Ch = 70%
Dh = 80%
Eh = 90%
Fh = 100%
12-10ACTIVE_BRAKE_MOD_INDEX_LIMITR/W0h Modulation index limit below which active braking will be applied
0h = 0%
1h = 40%
2h = 50%
3h = 60%
4h = 70%
5h = 80%
6h = 90%
7h = 100%
9SPEED_RANGE_SELR/W0h Frequency range selection for PWM duty mode reference input
0h = 325Hz to 100kHz
1h = 10Hz to 325Hz
8RESERVEDR0h Reserved
7-0RESERVEDR0h Reserved

6.7.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 10228100h]

GD_CONFIG1 is shown in Figure 6-77 and described in Table 6-40.

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Register to configure gated driver settings1

Figure 6-77 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R/W-0hR-0hR-0hR/W-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDRESERVED
R-0hR-0hR-0hR-0hR/W-0hR/W-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDOCP_DEGRESERVEDOCP_LVLOCP_MODE
R-0hR-0hR/W-0hR-0hR/W-0hR/W-1h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCSA_GAIN
R-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 6-40 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR0h Reserved
28RESERVEDR0h Reserved
27-26SLEW_RATER/W0h Slew rate
0h = Reserved
1h = Reserved
2h = Slew rate is 125 V/µs
3h = Slew rate is 200 V/µs
25-24RESERVEDR0h Reserved
23RESERVEDR0h Reserved
22RESERVEDR0h Reserved
21RESERVEDR0h Reserved
20RESERVEDR0h Reserved
19OVP_SELR/W0h Overvoltage level
0h = VM overvoltage level is 34-V
1h = VM overvoltage level is 22-V
18OVP_ENR/W0h Overvoltage enable
0h = Overvoltage protection is disabled
1h = Overvoltage protection is enabled
17RESERVEDR0h Reserved
16RESERVEDR0h Reserved
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13-12OCP_DEGR/W0h OCP deglitch time
0h = OCP deglitch time is 0.2 µs
1h = OCP deglitch time is 0.6 µs
2h = OCP deglitch time is 1.2 µs
3h = OCP deglitch time is 1.6 µs
11RESERVEDR0h Reserved
10OCP_LVLR/W0h Overcurrent level
0h = OCP level is 9 A (Typical)
1h = OCP level is 13 A (Typical)
9-8OCP_MODER/W1h OCP fault mode
0h = Overcurrent causes a latched fault
1h = Overcurrent causes an automatic retrying fault after 500ms
2h = Reserved
3h = Reserved
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3RESERVEDR0h Reserved
2RESERVEDR0h Reserved
1-0CSA_GAINR/W0h Current sense amplifier's gain (used only if DYNAMIC_CSA_GAIN_EN = 0)
0h = CSA gain is 0.24 V/A
1h = CSA gain is 0.48 V/A
2h = CSA gain is 0.96 V/A
3h = CSA gain is 1.92 V/A

6.7.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in Figure 6-78 and described in Table 6-41.

Return to the Summary Table.

Register to configure gated driver settings2

Figure 6-78 GD_CONFIG2 Register
3130292827262524
PARITYDELAY_COMP_ENTARGET_DELAYRESERVEDBUCK_PS_DIS
R/W-0hR/W-0hR/W-0hR-0hR/W1C-1h
2322212019181716
BUCK_CLBUCK_SELBUCK_DISMIN_ON_TIMERESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 6-41 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30DELAY_COMP_ENR/W0h Driver delay compensation enable
0h = Disable
1h = Enable
29-26TARGET_DELAYR/W0h Delay target for driver delay compensation
0h = Automatic based on slew rate
1h = 0.4 µs
2h = 0.6 µs
3h = 0.8 µs
4h = 1 µs
5h = 1.2 µs
6h = 1.4 µs
7h = 1.6 µs
8h = 1.8 µs
9h = 2 µs
Ah = 2.2 µs
Bh = 2.4 µs
Ch = 2.6 µs
Dh = 2.8 µs
Eh = 3 µs
Fh = 3.2 µs
25RESERVEDR0h Reserved
24BUCK_PS_DISR/W1C1h Buck power sequencing disable
0h = Buck power sequencing is enabled
1h = Buck power sequencing is disabled
23BUCK_CLR/W0h Buck current limit
0h = Buck regulator current limit is set to 600 mA
1h = Buck regulator current limit is set to 150 mA
22-21BUCK_SELR/W1h Buck output voltage
0h = Buck voltage is 3.3 V
1h = Buck voltage is 5.0 V
2h = Buck voltage is 4.0 V
3h = Buck voltage is 5.7 V
20BUCK_DISR/W0h Buck disable
0h = Buck regulator is enabled
1h = Buck regulator is disabled
19-17MIN_ON_TIMER/W0h Minimum ON time for low side MOSFET
0h = 0 µs
1h = Automatic based on slew rate
2h = 0.5 µs
3h = 0.75 µs
4h = 1 µs
5h = 1.25 µs
6h = 1.5 µs
7h = 2 µs
16-0RESERVEDR0h Reserved