JAJSR16 august   2023 MCF8316C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Reference Profiles
          2. 7.3.8.5.2 Staircase Speed Profile
          3. 7.3.8.5.3 Forward-Reverse Speed Profile
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Torque Mode
        5. 7.3.11.5 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Active Braking
      16. 7.3.16 Output PWM Switching Frequency
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Low-Side Braking
        3. 7.3.19.3 High-Side Braking
        4. 7.3.19.4 Active Spin-Down
        5. 7.3.19.5 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG during Open and Closed Loop States
        3. 7.3.20.3 FG during Fault and Idle States
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.22.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.22.10 FET Thermal Warning (OTW)
        11. 7.3.22.11 FET Thermal Shutdown (TSD_FET)
        12. 7.3.22.12 Motor Lock (MTR_LCK)
          1. 7.3.22.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.22.13 Motor Lock Detection
          1. 7.3.22.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.13.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.22.14 MPET Faults
        15. 7.3.22.15 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Anti voltage surge (AVS)
        6. 8.2.1.6 Real time variable tracking using DACOUT
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 サポート・リソース
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.3 Hardware_Configuration Registers

Table 7-34 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 7-34 should be considered as reserved locations and the register contents should not be modified.

Table 7-34 HARDWARE_CONFIGURATION Registers
Offset Acronym Register Name Section
A4h PIN_CONFIG Hardware Pin Configuration Go
A6h DEVICE_CONFIG1 Device configuration1 Go
A8h DEVICE_CONFIG2 Device configuration2 Go
AAh PERI_CONFIG1 Peripheral Configuration1 Go
ACh GD_CONFIG1 Gate Driver Configuration1 Go
AEh GD_CONFIG2 Gate Driver Configuration2 Go

Complex bit access types are encoded to fit into small table cells. Table 7-35 shows the codes that are used for access types in this section.

Table 7-35 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

7.7.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Figure 7-72 and described in Table 7-36.

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Register to configure hardware pins

Figure 7-72 PIN_CONFIG Register
3130292827262524
RESERVEDRESERVEDVdcFilterDisableRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDFG_IDLE_CONFIGFG_FAULT_CONFIG
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
FG_FAULT_CONFIGALARM_PIN_ENBRAKE_PIN_MODEALIGN_BRAKE_ANGLE_SELBRAKE_INPUTSPEED_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-36 PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30-28RESERVEDR/W0h Reserved
27VdcFilterDisableR/W0h Vdc (VM) filter disable
0h = Vdc filter Enable
1h = Vdc filter Disable
26-13RESERVEDR/W0h Reserved
12-11RESERVEDR/W0h Reserved
10-9FG_IDLE_CONFIGR/W0h FG configuration during stop
0h = FG state decided by FG_CONFIG
1h = FG is pulled to High
2h = FG is pulled to Low
3h = FG is pulled to High
8-7FG_FAULT_CONFIGR/W0h FG configuration during fault
0h = Use last FG Signal when motor is driven before fault
1h = FG is pulled to High
2h = FG is pulled to Low
3h = FG state decided by FG_CONFIG
6ALARM_PIN_ENR/W0h Alarm pin enable
0h = Disable
1h = Enable
5BRAKE_PIN_MODER/W0h Brake pin mode
0h = Low side brake
1h = Align brake
4ALIGN_BRAKE_ANGLE_SELR/W0h Align brake angle select
0h = Use last commutation angle before entering align braking
1h = Use ALIGN_ANGLE configuration for align braking
3-2BRAKE_INPUTR/W0h Brake pin override
0h = Hardware Pin BRAKE
1h = Override pin and brake/align according to BRAKE_PIN_MODE
2h = Override pin and do not brake/align
3h = Hardware Pin BRAKE
1-0SPEED_MODER/W0h Configure motor control input source
0h = Controlled by analog voltage on SPEED pin
1h = Controlled by duty cycle (PWM) on SPEED pin
2h = Controlled by DIGITAL_SPEED_CTRL value (I2C)
3h = Controlled by frequency on SPEED pin

7.7.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 00000000h]

DEVICE_CONFIG1 is shown in Figure 7-73 and described in Table 7-37.

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Register to configure device

Figure 7-73 DEVICE_CONFIG1 Register
3130292827262524
RESERVEDRESERVEDDAC_SOx_SELDAC_ENABLEI2C_TARGET_ADDR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
I2C_TARGET_ADDRRESERVED
R/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSLEW_RATE_I2C_PINSPULLUP_ENABLEBUS_VOLT
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-37 DEVICE_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30RESERVEDR/W0h Reserved
29-28DAC_SOx_SELR/W0h Selects between DAC2 and SOx channels
0h = DACOUT2
1h = SOA
2h = SOB
3h = SOC
27DAC_ENABLER/W0h DAC1 and DAC2 enables
0h = DACOUT1 and DACOUT2 on dedicated DAC pins disabled
1h = DACOUT1 and DACOUT2 on dedicated DAC pins enabled
26-20I2C_TARGET_ADDRR/W0h I2C target address
19-5RESERVEDR/W0h Reserved
4-3SLEW_RATE_I2C_PINSR/W0h Slew rate control for I2C pins
0h = 4.8 mA
1h = 3.9 mA
2h = 1.86 mA
3h = 30.8 mA
2PULLUP_ENABLER/W0h Pull-up enable for nFAULT and FG pins
0h = Disable
1h = Enable
1-0BUS_VOLTR/W0h Maximum DC bus voltage configuration
0h = 15 V
1h = 30 V
2h = 60 V
3h = Not defined

7.7.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Figure 7-74 and described in Table 7-38.

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Register to configure device

Figure 7-74 DEVICE_CONFIG2 Register
3130292827262524
RESERVEDINPUT_MAXIMUM_FREQ
R/W-0hR/W-0h
2322212019181716
INPUT_MAXIMUM_FREQ
R/W-0h
15141312111098
SLEEP_ENTRY_TIMEDYNAMIC_CSA_GAIN_ENDYNAMIC_VOLTAGE_GAIN_ENDEV_MODECLK_SELEXT_CLK_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EXT_CLK_CONFIGEXT_WDT_ENEXT_WDT_CONFIGEXT_WDT_INPUT_MODEEXT_WDT_FAULT_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-38 DEVICE_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30-16INPUT_MAXIMUM_FREQR/W0h Input frequency on speed pin for frequency based motor control that corresponds to 100% duty cycle. Input duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14SLEEP_ENTRY_TIMER/W0h Device enters sleep mode when input source is held at or below the sleep entry threshold for SLEEP_ENTRY_TIME
0h = Sleep entry when SPEED pin remains low for 50µs
1h = Sleep entry when SPEED pin remains low for 200µs
2h = Sleep entry when SPEED pin remains low for 20ms
3h = Sleep entry when SPEED pin remains low for 200ms
13DYNAMIC_CSA_GAIN_ENR/W0h Adjust CSA gain dynamically for optimal resolution across current levels
0h = Dynamic CSA gain is disabled
1h = Dynamic CSA gain is enabled
12DYNAMIC_VOLTAGE_GAIN_ENR/W0h Adjust voltage gain dynamically for optimal voltage resolution across voltage levels
0h = Dynamic voltage gain is disabled
1h = Dynamic voltage gain is enabled
11DEV_MODER/W0h Device mode select
0h = Standby Mode
1h = Sleep Mode
10-9CLK_SELR/W0h Clock source
0h = Internal Oscillator
1h = Crude Oscillator - WDT
2h = Not Applicable
3h = External Clock input
8EXT_CLK_ENR/W0h Enable external clock mode
0h = Disable
1h = Enable
7-5EXT_CLK_CONFIGR/W0h External clock configuration
0h = 8 kHz
1h = 16 kHz
2h = 32 kHz
3h = 64 kHz
4h = 128 kHz
5h = 256 kHz
6h = 512 kHz
7h = 1024 kHz
4EXT_WDT_ENR/W0h Enable external watchdog
0h = Disable
1h = Enable
3-2EXT_WDT_CONFIGR/W0h Time between watchdog tickles (GPIO/I2C)
0h = 100ms/1s
1h = 200ms/2s
2h = 500ms/5s
3h = 1000ms/10s
1EXT_WDT_INPUT_MODER/W0h External watchdog input mode
0h = Watchdog tickle over I2C
1h = Watchdog tickle over GPIO
0EXT_WDT_FAULT_MODER/W0h External watchdog fault mode
0h = Report Only
1h = Latch with FETs in Hi-Z

7.7.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 00000000h]

PERI_CONFIG1 is shown in Figure 7-75 and described in Table 7-39.

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Register to peripheral1

Figure 7-75 PERI_CONFIG1 Register
3130292827262524
RESERVEDSPREAD_SPECTRUM_MODULATION_DISRESERVEDBUS_CURRENT_LIMIT
R/W-0hR/W-1hR/W-0hR/W-0h
2322212019181716
BUS_CURRENT_LIMITBUS_CURRENT_LIMIT_ENABLEDIR_INPUTDIR_CHANGE_MODESELF_TEST_ENABLEACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYACTIVE_BRAKE_MOD_INDEX_LIMITSPEED_RANGE_SELRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R/W-0h
Table 7-39 PERI_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30SPREAD_SPECTRUM_MODULATION_DISR/W1h Spread Spectrum Modulation disable
0h = SSM is Enabled
1h = SSM is Disabled
29-26RESERVEDR/W0h Reserved
25-22BUS_CURRENT_LIMITR/W0h Bus current limit
0h = 0.125 A
1h = 0.25 A
2h = 0.5 A
3h = 1.0 A
4h = 1.5 A
5h = 2.0 A
6h = 2.5 A
7h = 3.0 A
8h = 3.5 A
9h = 4.0 A
Ah = 4.5 A
Bh = 5.0 A
Ch = 5.5 A
Dh = 6.0 A
Eh = 7.0 A
Fh = 8.0 A
21BUS_CURRENT_LIMIT_ENABLER/W0h Bus current limit enable
0h = Disable
1h = Enable
20-19DIR_INPUTR/W0h DIR pin override
0h = Hardware Pin DIR
1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC
2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB
3h = Hardware Pin DIR
18DIR_CHANGE_MODER/W0h Response to change of DIR pin status
0h = Follow motor stop options and ISD routine on detecting DIR change
1h = Change the direction through Reverse Drive while continuously driving the motor
17SELF_TEST_ENABLER/W0h Enables self-test on power up
0h = STL is disabled
1h = STL is enabled
16-13ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYR/W0h Difference between final speed and present speed below which active braking will be applied
0h = Not Applicable
1h = 5%
2h = 10%
3h = 15%
4h = 20%
5h = 25%
6h = 30%
7h = 35%
8h = 40%
9h = 45%
Ah = 50%
Bh = 60%
Ch = 70%
Dh = 80%
Eh = 90%
Fh = 100%
12-10ACTIVE_BRAKE_MOD_INDEX_LIMITR/W0h Modulation Index limit below which active braking will be applied
0h = 0%
1h = 40%
2h = 50%
3h = 60%
4h = 70%
5h = 80%
6h = 90%
7h = 100%
9SPEED_RANGE_SELR/W0h Frequency range selection for PWM/duty based motor control input
0h = 325Hz to 100kHz
1h = 10Hz to 325Hz
8RESERVEDR/W0h Reserved
7-0RESERVEDR/W0h Reserved

7.7.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 00000000h]

GD_CONFIG1 is shown in Figure 7-76 and described in Table 7-40.

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Register to configure gated driver settings1

Figure 7-76 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDOTW_REP
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
RESERVEDRESERVEDOCP_DEGRESERVEDOCP_LVLOCP_MODE
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCSA_GAIN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-40 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR/W0h Reserved
28RESERVEDR/W1h Reserved
27-26SLEW_RATER/W0h Slew rate
0h = Not Applicable
1h = Not Applicable
2h = Slew rate is 125 V/µs
3h = Slew rate is 200 V/µs
25-24RESERVEDR/W0h Reserved
23RESERVEDR/W0h Reserved
22RESERVEDR/W0h Reserved
21RESERVEDR/W1h Reserved
20RESERVEDR/W0h Reserved
19OVP_SELR/W0h Overvoltage level
0h = VM overvoltage level is 34-V
1h = VM overvoltage level is 22-V
18OVP_ENR/W0h Overvoltage enable
0h = Overvoltage protection is disabled
1h = Overvoltage protection is enabled
17RESERVEDR/W1h Reserved
16OTW_REPR/W0h Overtemperature warning enable
0h = Over temperature reporting on nFAULT is disabled
1h = Over temperature reporting on nFAULT is enabled
15RESERVEDR/W1h Reserved
14RESERVEDR/W0h Reserved
13-12OCP_DEGR/W0h OCP Deglitch Time Settings
0h = OCP deglitch time is 0.2 µs
1h = OCP deglitch time is 0.6 µs
2h = OCP deglitch time is 1.1 µs
3h = OCP deglitch time is 1.6 µs
11RESERVEDR/W0h Reserved
10OCP_LVLR/W0h Overcurrent Level Setting
0h = OCP level is 16 A (Typical)
1h = OCP level is 24 A (Typical)
9-8OCP_MODER/W1h OCP Fault Mode
0h = Overcurrent causes a latched fault
1h = Overcurrent causes an automatic retrying fault after 500ms
2h = Not Applicable
3h = Not Applicable
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1-0CSA_GAINR/W0h Current Sense Amplifier gain (used only if DYNAMIC_CSA_GAIN_EN = 0b)
0h = CSA gain is 0.15 V/A
1h = CSA gain is 0.3 V/A
2h = CSA gain is 0.6 V/A
3h = CSA gain is 1.2 V/A

7.7.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 00000000h]

GD_CONFIG2 is shown in Figure 7-77 and described in Table 7-41.

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Register to configure gated driver settings2

Figure 7-77 GD_CONFIG2 Register
3130292827262524
PARITYRESERVEDRESERVEDRESERVEDBUCK_PS_DIS
R/W-0hR/W-0hR/W-0hR/W-0hR/W1C-1h
2322212019181716
BUCK_CLBUCK_SELRESERVEDMIN_ON_TIMERESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 7-41 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30RESERVEDR/W0h Reserved
29-26RESERVEDR/W0h Reserved
25RESERVEDR/W0h Reserved
24BUCK_PS_DISR/W1C1h Buck power sequencing disable
0h = Buck power sequencing is enabled
1h = Buck power sequencing is disabled
23BUCK_CLR/W0h Buck current limit
0h = Buck regulator current limit is set to 600 mA
1h = Buck regulator current limit is set to 150 mA
22-21BUCK_SELR/W1h Buck voltage
0h = Buck voltage is 3.3 V
1h = Buck voltage is 5.0 V
2h = Buck voltage is 4.0 V
3h = Buck voltage is 5.7 V
20RESERVEDR/W0h Reserved
19-17MIN_ON_TIMER/W0h Minimum ON time for low side MOSFET
0h = 0 µs
1h = Automatic based on Slew rate
2h = 0.5 µs
3h = 0.75 µs
4h = 1 µs
5h = 1.25 µs
6h = 1.5 µs
7h = 2 µs
16-0RESERVEDR/W0h Reserved