JAJSG88D May   2013  – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 8.9  Inputs – Interrupts DVCC Domain Port P6 (P6.0 to P6.7)
    10. 8.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    11. 8.11 Leakage Current – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 8.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 8.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 8.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 8.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 8.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 8.17 Output Frequency – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 8.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 8.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 8.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 8.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 8.22 Crystal Oscillator, XT2
    23. 8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 8.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 8.25 DCO Frequency
    26. 8.26 PMM, Brownout Reset (BOR)
    27. 8.27 PMM, Core Voltage
    28. 8.28 PMM, SVS High Side
    29. 8.29 PMM, SVM High Side
    30. 8.30 PMM, SVS Low Side
    31. 8.31 PMM, SVM Low Side
    32. 8.32 Wake-up Times From Low-Power Modes and Reset
    33. 8.33 Timer_A
    34. 8.34 Timer_B
    35. 8.35 USCI (UART Mode) Clock Frequency
    36. 8.36 USCI (UART Mode)
    37. 8.37 USCI (SPI Master Mode) Clock Frequency
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 8.42 10-Bit ADC, Timing Parameters
    43. 8.43 10-Bit ADC, Linearity Parameters
    44. 8.44 REF, External Reference
    45. 8.45 REF, Built-In Reference
    46. 8.46 Comparator_B
    47. 8.47 Flash Memory
    48. 8.48 JTAG and Spy-Bi-Wire Interface
    49. 8.49 DVIO BSL Entry
  9. Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
      1. 9.5.1 Bootloader – I2C
      2. 9.5.2 Bootloader – UART
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC10_A
      17. 9.9.17 CRC16
      18. 9.9.18 Reference (REF) Module Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM) (S Version)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      10. 9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  サポート・リソース
    7. 10.7  Trademarks
    8. 10.8  静電気放電に関する注意事項
    9. 10.9  Export Control Notice
    10. 10.10 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-1). The vector contains the 16-bit address of the interrupt-handler instruction sequence.

Table 9-1 Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORD ADDRESSPRIORITY
System Reset
Power up
External reset
Watchdog time-out, password violation
Flash memory password violation
PMM password violation
WDTIFG, KEYV (SYSRSTIV)(1) (3)Reset0FFFEh63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(1)(Non)maskable0FFFCh62
User NMI
NMI
Oscillator fault
Flash memory access violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1) (3)(Non)maskable0FFFAh61
COMP_BComparator B interrupt flags (CBIV)(1) (2)Maskable0FFF8h60
USCI_A0 receive or transmitUCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)Maskable0FFF6h59
USCI_B0 receive or transmitUCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)Maskable0FFF4h58
Watchdog timer interval timer modeWDTIFGMaskable0FFF2h57
USCI_A1 receive or transmitUCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)Maskable0FFF0h56
USCI_B1 receive or transmitUCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)Maskable0FFEEh55
ADC10_AADC10IFG0(1) (2) (5)Maskable0FFECh54
USCI_A2 receive or transmitUCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (2)Maskable0FFEAh53
USCI_B2 receive or transmitUCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (2)Maskable0FFE8h52
TA0TA0CCR0 CCIFG0(2)Maskable0FFE6h51
TA0TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
Maskable0FFE4h50
ReservedReserved(4)Maskable0FFE2h49
DMADMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (2)Maskable0FFE0h48
USCI_A3 receive or transmitUCA3RXIFG, UCA3TXIFG (UCA3IV)(1) (2)Maskable0FFDEh47
USCI_B3 receive or transmitUCB3RXIFG, UCB3TXIFG (UCB3IV)(1) (2)Maskable0FFDCh46
TB0TB0CCR0 CCIFG0 (2)Maskable0FFDAh45
TB0TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1) (2)
Maskable0FFD8h44
TA1TA1CCR0 CCIFG0(2)Maskable0FFD6h43
TA1TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
Maskable0FFD4h42
I/O port P1P1IFG.0 to P1IFG.7 (P1IV)(1) (2)Maskable0FFD2h41
TA2TA2CCR0 CCIFG0(2)Maskable0FFD0h40
TA2TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
Maskable0FFCEh39
I/O port P2P2IFG.0 to P2IFG.7 (P2IV)(1) (2)Maskable0FFCCh38
RTC_ARTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(1) (2)Maskable0FFCAh37
I/O Port P6P6IFG.0 to P6IFG.7 (P6IV)(1) (2)Maskable0FFC8h36
ReservedReserved(4)0FFC6h35
0FF80h0, lowest
Multiple source flags
Interrupt flags are in the module.
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.
Only on devices with ADC, otherwise reserved