JAJSGB7A February   2015  – October 2018 MSP430F67621A , MSP430F67641A

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 アプリケーション図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions – PZ Package
      2. Table 4-4 Signal Descriptions – PN Package
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1  Power Supply Sequencing
      2. 5.8.2  Reset Timing
        1. Table 5-1 Wake-up Times From Low-Power Modes and Reset
      3. 5.8.3  Clock Specifications
        1. Table 5-2 Crystal Oscillator, XT1, Low-Frequency Mode
        2. Table 5-3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        3. Table 5-4 Internal Reference, Low-Frequency Oscillator (REFO)
        4. Table 5-5 DCO Frequency
      4. 5.8.4  Digital I/O Ports
        1. Table 5-6  Schmitt-Trigger Inputs, General-Purpose I/O
        2. Table 5-7  Inputs, Ports P1 and P2
        3. Table 5-8  Leakage Current, General-Purpose I/O
        4. Table 5-9  Outputs, General-Purpose I/O (Full Drive Strength)
        5. 5.8.4.1    Typical Characteristics, General-Purpose I/O (Full Drive Strength)
        6. Table 5-10 Outputs, General-Purpose I/O (Reduced Drive Strength)
        7. 5.8.4.2    Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)
        8. Table 5-11 Output Frequency, General-Purpose I/O
      5. 5.8.5  Power-Management Module (PMM)
        1. Table 5-12 PMM, Brownout Reset (BOR)
        2. Table 5-13 PMM, Core Voltage
        3. Table 5-14 PMM, SVS High Side
        4. Table 5-15 PMM, SVM High Side
        5. Table 5-16 PMM, SVS Low Side
        6. Table 5-17 PMM, SVM Low Side
      6. 5.8.6  Auxiliary Supplies Module
        1. Table 5-18 Auxiliary Supplies, Recommended Operating Conditions
        2. Table 5-19 Auxiliary Supplies, AUX3 (Backup Subsystem) Currents
        3. Table 5-20 Auxiliary Supplies, Auxiliary Supply Monitor
        4. Table 5-21 Auxiliary Supplies, Switch ON-Resistance
        5. Table 5-22 Auxiliary Supplies, Switching Time
        6. Table 5-23 Auxiliary Supplies, Switch Leakage
        7. Table 5-24 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
        8. Table 5-25 Auxiliary Supplies, Charge-Limiting Resistor
      7. 5.8.7  Timer_A Module
        1. Table 5-26 Timer_A
      8. 5.8.8  eUSCI Module
        1. Table 5-27 eUSCI (UART Mode) Clock Frequency
        2. Table 5-28 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-29 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-30 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-31 eUSCI (SPI Slave Mode)
        6. Table 5-32 eUSCI (I2C Mode)
      9. 5.8.9  LCD Controller
        1. Table 5-33 LCD_C Operating Conditions
        2. Table 5-34 LCD_C Electrical Characteristics
      10. 5.8.10 SD24_B Module
        1. Table 5-35 SD24_B Power Supply and Recommended Operating Conditions
        2. Table 5-36 SD24_B Analog Input
        3. Table 5-37 SD24_B Supply Currents
        4. Table 5-38 SD24_B Performance
        5. Table 5-39 SD24_B AC Performance
        6. Table 5-40 SD24_B AC Performance
        7. Table 5-41 SD24_B AC Performance
        8. Table 5-42 SD24_B External Reference Input
      11. 5.8.11 ADC10_A Module
        1. Table 5-43 10-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-44 10-Bit ADC, Timing Parameters
        3. Table 5-45 10-Bit ADC, Linearity Parameters
        4. Table 5-46 10-Bit ADC, External Reference
      12. 5.8.12 REF Module
        1. Table 5-47 REF, Built-In Reference
      13. 5.8.13 Flash
        1. Table 5-48 Flash Memory
      14. 5.8.14 Emulation and Debug
        1. Table 5-49 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagrams
    3. 6.3  CPU
    4. 6.4  Instruction Set
    5. 6.5  Operating Modes
    6. 6.6  Interrupt Vector Addresses
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 RAM
    11. 6.11 Backup RAM
    12. 6.12 Peripherals
      1. 6.12.1  Oscillator and System Clock
      2. 6.12.2  Power-Management Module (PMM)
      3. 6.12.3  Auxiliary Supply System
      4. 6.12.4  Backup Subsystem
      5. 6.12.5  Digital I/O
      6. 6.12.6  Port Mapping Controller
      7. 6.12.7  System Module (SYS)
      8. 6.12.8  Watchdog Timer (WDT_A)
      9. 6.12.9  DMA Controller
      10. 6.12.10 CRC16
      11. 6.12.11 Hardware Multiplier
      12. 6.12.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.12.13 ADC10_A
      14. 6.12.14 SD24_B
      15. 6.12.15 TA0
      16. 6.12.16 TA1
      17. 6.12.17 TA2
      18. 6.12.18 TA3
      19. 6.12.19 SD24_B Triggers
      20. 6.12.20 ADC10_A Triggers
      21. 6.12.21 Real-Time Clock (RTC_C)
      22. 6.12.22 Reference (REF) Module Voltage Reference
      23. 6.12.23 LCD_C
      24. 6.12.24 Embedded Emulation Module (EEM) (S Version)
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      2. 6.13.2  Port P1 (P1.2) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
      6. 6.13.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (PZ Package Only)
      7. 6.13.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
      8. 6.13.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (PZ Package Only)
      9. 6.13.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (PZ Package Only)
      10. 6.13.10 Port P9 (P9.0), Input/Output With Schmitt Trigger (PZ Package Only)
      11. 6.13.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (PZ Package Only)
      12. 6.13.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (PN Package Only)
      13. 6.13.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PN Package Only)
      14. 6.13.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PN Package Only)
      15. 6.13.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PN Package Only)
      16. 6.13.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.13.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 6.14 Device Descriptors (TLV)
    15. 6.15 Memory
      1. 6.15.1 Peripheral File Map
    16. 6.16 Identification
      1. 6.16.1 Revision Identification
      2. 6.16.2 Device Identification
      3. 6.16.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  Device Nomenclature
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Attributes

Table 4-1 lists the pin attributes for the PZ package. See Table 4-2 for the PN package.

Table 4-1 Pin Attributes, PZ Package

PIN NO. SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE RESET STATE AFTER BOR(5)
1 SD0P0 I Analog AVCC OFF
2 SD0N0 I Analog AVCC OFF
3 SD1P0 I Analog AVCC OFF
4 SD1N0 I Analog AVCC OFF
5 SD2P0 I Analog AVCC OFF
6 SD2N0 I Analog AVCC OFF
7 VREF I Analog AVCC OFF
8 AVSS P Power N/A
9 AVCC P Power N/A
10 VASYS P Power N/A
11 P9.1 I/O LVCMOS DVCC OFF
A5 I Analog AVCC
12 P9.2 I/O LVCMOS DVCC OFF
A4 I Analog AVCC
13 P9.3 I/O LVCMOS DVCC OFF
A3 I Analog AVCC
14 P1.0 I/O LVCMOS DVCC OFF
PM_TA0.0 I/O LVCMOS DVCC
VeREF- I Analog AVCC
A2 I LVCMOS DVCC
15 P1.1 I/O LVCMOS DVCC OFF
PM_TA0.1 I/O LVCMOS DVCC
VeREF+ I LVCMOS DVCC
A1 I Analog AVCC
16 P1.2 I/O LVCMOS DVCC OFF
PM_UCA0RXD I LVCMOS DVCC
PM_UCA0SOMI I/O LVCMOS DVCC
A0 I Analog AVCC
17 P1.3 I/O LVCMOS DVCC OFF
PM_UCA0TXD O LVCMOS DVCC
PM_UCA0SIMO I/O LVCMOS DVCC
R03 I/O Analog AVCC
18 AUXVCC2 P Power N/A
19 AUXVCC1 P Power N/A
20 VDSYS P Power N/A
21 DVCC P Power N/A
22 DVSS P Power N/A
23 VCORE P Power N/A
24 XIN I LVCMOS DVCC OFF
25 XOUT O LVCMOS DVCC OFF
26 AUXVCC3 P Power N/A
27 P1.4 I/O LVCMOS DVCC OFF
PM_UCA1RXD I LVCMOS DVCC
PM_UCA1SOMI I/O LVCMOS DVCC
LCDREF I Analog AVCC
R13 I/O Analog AVCC
28 P1.5 I/O LVCMOS DVCC OFF
PM_UCA1TXD O LVCMOS DVCC
PM_UCA1SIMO I/O LVCMOS DVCC
R23 I/O Analog AVCC
29 LCDCAP I/O Analog AVCC OFF
R33 I/O Analog AVCC
30 P8.4 I/O LVCMOS DVCC OFF
TA1.0 I/O LVCMOS DVCC
31 P8.5 I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC
32 COM0 O LVCMOS DVCC OFF
33 COM1 O LVCMOS DVCC OFF
34 COM2 O LVCMOS DVCC OFF
35 COM3 O LVCMOS DVCC OFF
36 P1.6 I/O LVCMOS DVCC OFF
PM_UCA0CLK I/O LVCMOS DVCC
COM4 O LVCMOS DVCC
37 P1.7 I/O LVCMOS DVCC OFF
PM_UCB0CLK I/O LVCMOS DVCC
COM5 O LVCMOS DVCC
38 P2.0 I/O LVCMOS DVCC OFF
PM_UCB0SOMI I/O LVCMOS DVCC
PM_UCB0SCL I/O LVCMOS DVCC
COM6 O LVCMOS DVCC
39 P2.1 I/O LVCMOS DVCC OFF
PM_UCB0SIMO I/O LVCMOS DVCC
PM_UCB0SDA I/O LVCMOS DVCC
COM7 O LVCMOS DVCC
40 P8.6 I/O LVCMOS DVCC OFF
TA2.0 I/O LVCMOS DVCC
41 P8.7 I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC
42 P9.0 I/O LVCMOS DVCC OFF
TACLK I LVCMOS DVCC
RTCCLK O LVCMOS DVCC
43 P2.2 I/O LVCMOS DVCC OFF
PM_UCA2RXD I LVCMOS DVCC
PM_UCA2SOMI I/O LVCMOS DVCC
44 P2.3 I/O LVCMOS DVCC OFF
PM_UCA2TXD O LVCMOS DVCC
PM_UCA2SIMO I/O LVCMOS DVCC
45 P2.4 I/O LVCMOS DVCC OFF
PM_UCA1CLK I/O LVCMOS DVCC
46 P2.5 I/O LVCMOS DVCC OFF
PM_UCA2CLK I/O LVCMOS DVCC
47 P2.6 I/O LVCMOS DVCC OFF
PM_TA1.0 I/O LVCMOS DVCC
48 P2.7 I/O LVCMOS DVCC OFF
PM_TA1.1 I/O LVCMOS DVCC
49 P3.0 I/O LVCMOS DVCC OFF
PM_TA2.0 I/O LVCMOS DVCC
BSL_TX O LVCMOS DVCC
50 P3.1 I/O LVCMOS DVCC OFF
PM_TA2.1 I/O LVCMOS DVCC
BSL_RX I LVCMOS DVCC
51 P3.2 I/O LVCMOS DVCC OFF
PM_TACLK I LVCMOS DVCC
PM_RTCCLK O LVCMOS DVCC
52 P3.3 I/O LVCMOS DVCC OFF
PM_TA0.2 I/O LVCMOS DVCC
53 P3.4 I/O LVCMOS DVCC OFF
PM_SDCLK I/O LVCMOS DVCC
S39 O LVCMOS DVCC
54 P3.5 I/O LVCMOS DVCC OFF
PM_SD0DIO I/O LVCMOS DVCC
S38 O LVCMOS DVCC
55 P3.6 I/O LVCMOS DVCC OFF
PM_SD1DIO I/O LVCMOS DVCC
S37 O LVCMOS DVCC
56 P3.7 I/O LVCMOS DVCC OFF
PM_SD2DIO I/O LVCMOS DVCC
S36 O LVCMOS DVCC
57 P4.0 I/O LVCMOS DVCC OFF
S35 O LVCMOS DVCC
58 P4.1 I/O LVCMOS DVCC OFF
S34 O LVCMOS DVCC
59 P4.2 I/O LVCMOS DVCC OFF
S33 O LVCMOS DVCC
60 P4.3 I/O LVCMOS DVCC OFF
S32 O LVCMOS DVCC
61 P4.4 I/O LVCMOS DVCC OFF
S31 O LVCMOS DVCC
62 P4.5 I/O LVCMOS DVCC OFF
S30 O LVCMOS DVCC
63 P4.6 I/O LVCMOS DVCC OFF
S29 O LVCMOS DVCC
64 P4.7 I/O LVCMOS DVCC OFF
S28 O LVCMOS DVCC
65 P5.0 I/O LVCMOS DVCC OFF
S27 O LVCMOS DVCC
66 P5.1 I/O LVCMOS DVCC OFF
S26 O LVCMOS DVCC
67 P5.2 I/O LVCMOS DVCC OFF
S25 O LVCMOS DVCC
68 P5.3 I/O LVCMOS DVCC OFF
S24 O LVCMOS DVCC
69 P5.4 I/O LVCMOS DVCC OFF
S23 O LVCMOS DVCC
70 P5.5 I/O LVCMOS DVCC OFF
S22 O LVCMOS DVCC
71 P5.6 I/O LVCMOS DVCC OFF
S21 O LVCMOS DVCC
72 P5.7 I/O LVCMOS DVCC OFF
S20 O LVCMOS DVCC
73 P6.0 I/O LVCMOS DVCC OFF
S19 O LVCMOS DVCC
74 DVSYS P Power N/A
75 DVSS P Power N/A
76 P6.1 I/O LVCMOS DVCC OFF
S18 O LVCMOS DVCC
77 P6.2 I/O LVCMOS DVCC OFF
S17 O LVCMOS DVCC
78 P6.3 I/O LVCMOS DVCC OFF
S16 O LVCMOS DVCC
79 P6.4 I/O LVCMOS DVCC OFF
S15 O LVCMOS DVCC
80 P6.5 I/O LVCMOS DVCC OFF
S14 O LVCMOS DVCC
81 P6.6 I/O LVCMOS DVCC OFF
S13 O LVCMOS DVCC
82 P6.7 I/O LVCMOS DVCC OFF
S12 O LVCMOS DVCC
83 P7.0 I/O LVCMOS DVCC OFF
S11 O LVCMOS DVCC
84 P7.1 I/O LVCMOS DVCC OFF
S10 O LVCMOS DVCC
85 P7.2 I/O LVCMOS DVCC OFF
S9 O LVCMOS DVCC
86 P7.3 I/O LVCMOS DVCC OFF
S8 O LVCMOS DVCC
87 P7.4 I/O LVCMOS DVCC OFF
S7 O LVCMOS DVCC
88 P7.5 I/O LVCMOS DVCC OFF
S6 O LVCMOS DVCC
89 P7.6 I/O LVCMOS DVCC OFF
S5 O LVCMOS DVCC
90 P7.7 I/O LVCMOS DVCC OFF
S4 O LVCMOS DVCC
91 P8.0 I/O LVCMOS DVCC OFF
S3 O LVCMOS DVCC
92 P8.1 I/O LVCMOS DVCC OFF
S2 O LVCMOS DVCC
93 P8.2 I/O LVCMOS DVCC OFF
S1 O LVCMOS DVCC
94 P8.3 I/O LVCMOS DVCC OFF
S0 O LVCMOS DVCC
95 TEST I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC
96 PJ.0 I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC
TDO O LVCMOS DVCC
97 PJ.1 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
98 PJ.2 I/O LVCMOS DVCC OFF
ADC10CLK O LVCMOS DVCC
TMS I LVCMOS DVCC
99 PJ.3 I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC
TCK I LVCMOS DVCC
100 RST I LVCMOS DVCC PU
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
For each multiplexed pin, the signal that is listed first in this table is the reset default.
Signal Types: I = Input, O = Output, I/O = Input or Output
Buffer Types: LVCMOS, Analog, or Power (see Table 4-5, Buffer Type)
To determine the pin mux encodings for each pin, refer to Section 6.13, Input/Ouput Schematics.
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
PU = High-impedance input with pullup enabled
N/A = Not applicable

Table 4-2 lists the pin attributes for the PN package. See Table 4-1 for the PZ package.

Table 4-2 Pin Attributes, PN Package

PIN NO. SIGNAL NAME (1)(4) SIGNAL TYPE (2) BUFFER TYPE (3) POWER SOURCE RESET STATE AFTER BOR (5)
1 SD0P0 I Analog AVCC OFF
2 SD0N0 I Analog AVCC OFF
3 SD1P0 I Analog AVCC OFF
4 SD1N0 I Analog AVCC OFF
5 SD2P0 I Analog AVCC OFF
6 SD2N0 I Analog AVCC OFF
7 VREF I Analog AVCC OFF
8 AVSS P Power N/A
9 AVCC P Power N/A
10 VASYS P Power N/A
11 P1.0 I/O LVCMOS DVCC OFF
PM_TA0.0 I/O LVCMOS DVCC
VeREF- I Power
A2 I Analog AVCC
12 P1.1 I/O LVCMOS DVCC OFF
PM_TA0.1 I/O LVCMOS DVCC
VeREF+ I Power
A1 I Analog AVCC
13 P1.2 I/O LVCMOS DVCC OFF
PM_UCA0RXD I LVCMOS DVCC
PM_UCA0SOMI I/O LVCMOS DVCC
A0 I Analog AVCC
14 P1.3 I/O LVCMOS DVCC OFF
PM_UCA0TXD O LVCMOS DVCC
PM_UCA0SIMO I/O LVCMOS DVCC
R03 I/O Analog AVCC
15 AUXVCC2 P Power N/A
16 AUXVCC1 P Power N/A
17 VDSYS P Power N/A
18 DVCC P Power N/A
19 DVSS P Power N/A
20 VCORE P Power N/A
21 XIN I LVCMOS DVCC OFF
22 XOUT O LVCMOS DVCC OFF
23 AUXVCC3 P Power N/A
24 P1.4 I/O LVCMOS DVCC OFF
PM_UCA1RXD I LVCMOS DVCC
PM_UCA1SOMI I/O LVCMOS DVCC
LCDREF I Analog AVCC
R13 I/O Analog AVCC
25 P1.5 I/O LVCMOS DVCC OFF
PM_UCA1TXD O LVCMOS DVCC
PM_UCA1SIMO I/O LVCMOS DVCC
R23 I/O Analog AVCC
26 LCDCAP I/O Analog AVCC OFF
R33 I/O Analog AVCC OFF
27 COM0 O LVCMOS DVCC OFF
28 COM1 O LVCMOS DVCC OFF
29 COM2 O LVCMOS DVCC OFF
30 COM3 O LVCMOS DVCC OFF
31 P1.6 I/O LVCMOS DVCC OFF
PM_UCA0CLK I/O LVCMOS DVCC
COM4 O LVCMOS DVCC
32 P1.7 I/O LVCMOS DVCC OFF
PM_UCB0CLK I/O LVCMOS DVCC
COM5 O LVCMOS DVCC
33 P2.0 I/O LVCMOS DVCC OFF
PM_UCB0SOMI I/O LVCMOS DVCC
PM_UCB0SCL I/O LVCMOS DVCC
COM6 O LVCMOS DVCC
S39 O LVCMOS DVCC
34 P2.1 I/O LVCMOS DVCC OFF
PM_UCB0SIMO I/O LVCMOS DVCC
PM_UCB0SDA I/O LVCMOS DVCC
COM7 O LVCMOS DVCC
S38 O LVCMOS DVCC
35 P2.2 I/O LVCMOS DVCC OFF
PM_UCA2RXD I LVCMOS DVCC -
PM_UCA2SOMI I/O LVCMOS DVCC -
S37 O LVCMOS DVCC -
36 P2.3 I/O LVCMOS DVCC OFF
PM_UCA2TXD O LVCMOS DVCC
PM_UCA2SIMO I/O LVCMOS DVCC
S36 O LVCMOS DVCC
37 P2.4 I/O LVCMOS DVCC OFF
PM_UCA1CLK I/O LVCMOS DVCC
S35 O LVCMOS DVCC
38 P2.5 I/O LVCMOS DVCC OFF
PM_UCA2CLK I/O LVCMOS DVCC
S34 O LVCMOS DVCC
39 P2.6 I/O LVCMOS DVCC OFF
PM_TA1.0 I/O LVCMOS DVCC
S33 O LVCMOS DVCC
40 P2.7 I/O LVCMOS DVCC OFF
PM_TA1.1 I/O LVCMOS DVCC
S32 O LVCMOS DVCC
41 P3.0 I/O LVCMOS DVCC OFF
PM_TA2.0 I/O LVCMOS DVCC
S31 O LVCMOS DVCC
BSL_TX O LVCMOS DVCC
42 P3.1 I/O LVCMOS DVCC OFF
PM_TA2.1 I/O LVCMOS DVCC
S30 O LVCMOS DVCC
BSL_RX I LVCMOS DVCC
43 P3.2 I/O LVCMOS DVCC OFF
PM_TACLK I LVCMOS DVCC
PM_RTCCLK O LVCMOS DVCC
S29 O LVCMOS DVCC
44 P3.3 I/O LVCMOS DVCC OFF
PM_TA0.2 I/O LVCMOS DVCC
S28 O LVCMOS DVCC
45 P3.4 I/O LVCMOS DVCC OFF
PM_SDCLK I/O LVCMOS DVCC
S27 O LVCMOS DVCC
46 P3.5 I/O LVCMOS DVCC OFF
PM_SD0DIO I/O LVCMOS DVCC
S26 O LVCMOS DVCC
47 P3.6 I/O LVCMOS DVCC OFF
PM_SD1DIO I/O LVCMOS DVCC
S25 O LVCMOS DVCC
48 P3.7 I/O LVCMOS DVCC OFF
PM_SD2DIO I/O LVCMOS DVCC
S24 O LVCMOS DVCC
49 P4.0 I/O LVCMOS DVCC OFF
S23 O LVCMOS DVCC
50 P4.1 I/O LVCMOS DVCC OFF
S22 O LVCMOS DVCC
51 P4.2 I/O LVCMOS DVCC OFF
S21 O LVCMOS DVCC
52 P4.3 I/O LVCMOS DVCC OFF
S20 O LVCMOS DVCC
53 P4.4 I/O LVCMOS DVCC OFF
S19 O LVCMOS DVCC
54 P4.5 I/O LVCMOS DVCC OFF
S18 O LVCMOS DVCC
55 P4.6 I/O LVCMOS DVCC OFF
S17 O LVCMOS DVCC
56 P4.7 I/O LVCMOS DVCC OFF
S16 O LVCMOS DVCC
57 P5.0 I/O LVCMOS DVCC OFF
S15 O LVCMOS DVCC
58 P5.1 I/O LVCMOS DVCC OFF
S14 O LVCMOS DVCC
59 DVSYS P Power N/A
60 DVSS P Power N/A
61 P5.2 I/O LVCMOS DVCC OFF
S13 O LVCMOS DVCC
62 P5.3 I/O LVCMOS DVCC OFF
S12 O LVCMOS DVCC
63 P5.4 I/O LVCMOS DVCC OFF
S11 O LVCMOS DVCC
64 P5.5 I/O LVCMOS DVCC OFF
S10 O LVCMOS DVCC
65 P5.6 I/O LVCMOS DVCC OFF
S9 O LVCMOS DVCC
66 P5.7 I/O LVCMOS DVCC OFF
S8 O LVCMOS DVCC
67 P6.0 I/O LVCMOS DVCC OFF
S7 O LVCMOS DVCC
68 P6.1 I/O LVCMOS DVCC OFF
S6 O LVCMOS DVCC
69 P6.2 I/O LVCMOS DVCC OFF
S5 O LVCMOS DVCC
70 P6.3 I/O LVCMOS DVCC OFF
S4 O LVCMOS DVCC
71 P6.4 I/O LVCMOS DVCC OFF
S3 O LVCMOS DVCC
72 P6.5 I/O LVCMOS DVCC OFF
S2 O LVCMOS DVCC
73 P6.6 I/O LVCMOS DVCC OFF
S1 O LVCMOS DVCC
74 P6.7 I/O LVCMOS DVCC OFF
S0 O LVCMOS DVCC
75 TEST I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC
76 PJ.0 I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC
TDO O LVCMOS DVCC
77 PJ.1 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
78 PJ.2 I/O LVCMOS DVCC OFF
ADC10CLK O LVCMOS DVCC
TMS I LVCMOS DVCC
79 PJ.3 I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC
TCK I LVCMOS DVCC
80 RST I LVCMOS DVCC PU
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
For each multiplexed pin, the signal that is listed first in this table is the reset default.
Signal Types: I = Input, O = Output, I/O = Input or Output
Buffer Types: LVCMOS, Analog, or Power (see Table 4-5, Buffer Type)
To determine the pin mux encodings for each pin, refer to Section 6.13, Input/Ouput Schematics.
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
PU = High-impedance input with pullup enabled
N/A = Not applicable