JAJSCO8C November   2016  – October 2019 MUX36D08 , MUX36S16

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      リーク電流と温度
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions, MUX36S16
    2.     Pin Functions: MUX36D08
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Dual Supply
    6. 6.6 Electrical Characteristics: Single Supply
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Truth Tables
      1. 7.1.1  On-Resistance
      2. 7.1.2  Off Leakage
      3. 7.1.3  On-Leakage Current
      4. 7.1.4  Differential On-Leakage Current
      5. 7.1.5  Transition Time
      6. 7.1.6  Break-Before-Make Delay
      7. 7.1.7  Turn-On and Turn-Off Time
      8. 7.1.8  Charge Injection
      9. 7.1.9  Off Isolation
      10. 7.1.10 Channel-to-Channel Crosstalk
      11. 7.1.11 Bandwidth
      12. 7.1.12 THD + Noise
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultralow Leakage Current
      2. 8.3.2 Ultralow Charge Injection
      3. 8.3.3 Bidirectional Operation
      4. 8.3.4 Rail-to-Rail Operation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics: Dual Supply

at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG SWITCH
Analog signal range TA = –40°C to +125°C VSS VDD V
RON On-resistance VS = 0 V, IS = –1 mA 125 170 Ω
VS = ±10 V, IS = –1 mA 145 200
TA = –40°C to +85°C 230
TA = –40°C to +125°C 250
ΔRON On-resistance mismatch between channels VS = ±10 V, IS = –1 mA 6 9 Ω
TA = –40°C to +85°C 14
TA = –40°C to +125°C 16
RFLAT On-resistance flatness VS = 10 V, 0 V, –10 V 20 45 Ω
TA = –40°C to +85°C 53
TA = –40°C to +125°C 58
On-resistance drift VS = 0 V 0.62 Ω/°C
IS(OFF) Input leakage current Switch state is off,
VS = ±10 V, VD = ±10 V(2) 		–0.04 0.001 0.04 nA
TA = –40°C to +85°C –0.15 0.15
TA = –40°C to +125°C –1.2 1.2
ID(OFF) Output off-leakage current Switch state is off,
VS = ±10 V, VD = ±10 V(2) 		–0.15 0.01 0.15 nA
TA = -40°C to +85°C –1 1
TA = -40°C to +125°C –4.5 4.5
ID(ON) Output on-leakage current Switch state is on,
VD = ±10 V, VS = floating		 –0.2 0.01 0.2 nA
TA = –40°C to +85°C –1 1
TA = –40°C to +125°C –5.3 5.3
IDL(ON) Differential on-leakage current Switch state is on,
VDA = VDB = ±10 V, VS = floating		 –15 3 15 pA
TA = –40°C to +85°C –100 100
TA = –40°C to +125°C –500 500
LOGIC INPUT
VIH Logic voltage high 2 V
VIL Logic voltage low 0.8 V
ID Input current 0.1 µA
SWITCH DYNAMICS(1)
tON Enable turn-on time VS = ±10 V, RL = 300 Ω,
CL= 35 pF		 82 136 ns
TA = –40°C to +85°C 145
TA = –40°C to +125°C 151
tOFF Enable turn-off time VS = ±10 V, RL = 300 Ω,
CL= 35 pF		 63 78 ns
TA = –40°C to +85°C 89
TA = –40°C to +125°C 97
tt Transition time VS = 10 V, RL = 300 Ω,
CL= 35 pF, 		97 143 ns
TA = –40°C to +85°C 151
TA = –40°C to +125°C 157
tBBM Break-before-make time delay VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C 30 54 ns
QJ Charge injection CL = 1 nF, RS = 0 Ω VS = 0 V TSSOP package 0.31 pC
SOIC package 0.67
VS = –15 V to +15 V TSSOP package ±0.9
SOIC package ±1.1
Off-isolation RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz 		Nonadjacent channel to D, DA, DB TSSOP package –98 dB
SOIC package –94
Adjacent channel to D, DA, DB TSSOP package –94
SOIC package –88
Channel-to-channel crosstalk RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz		 Nonadjacent channels TSSOP package –100 dB
SOIC package –96
Adjacent channels TSSOP package –88
SOIC package –83
BW –3dB Bandwidth VS =  1 VRMS, RL  =  50 Ω , CL = 5 pF MUX36S16 260 dB
MUX36D08 430
THD + N Total harmonic distortion plus noise VS =  0 V or VDD, RL  =  600 Ω , CL = 50 pF, f = 20Hz to 20kHz 0.09%
CIN Digital input capacitance VIN = 0 V or VDD 1.1 pF
CS(OFF) Input off-capacitance f = 1 MHz, VS = 0 V 2.1 3 pF
CD(OFF) Output off-capacitance f = 1 MHz, VS = 0 V MUX36S16 11.1 12.2 pF
MUX36D08 6.4 7.5
CS(ON), CD(ON) Output on-capacitance f = 1 MHz, VS = 0 V MUX36S16 13.5 15 pF
MUX36D08 8.7 10.2
POWER SUPPLY
VDD supply current All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V, 		45 59 µA
TA = –40°C to +85°C 62
TA = –40°C to +125°C 69
VSS supply current All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V, 		26 33 µA
TA = –40°C to +85°C 36
TA = –40°C to +125°C 43
(1) Specified by design; not subject to production testing.
(2) When VS is positive, VD is negative, and vice versa.