SLLSEJ3A June   2015  – July 2015 ONET1130EC

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Transmitter AC Electrical Characteristics
    7. 7.7 Receiver AC Electrical Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmitter
        1. 8.3.1.1 Equalizer
        2. 8.3.1.2 CDR
        3. 8.3.1.3 Modulator Driver
        4. 8.3.1.4 Modulation Current Generator
        5. 8.3.1.5 DC Offset Cancellation and Cross Point Control
        6. 8.3.1.6 Transmitter Loopback (Electrical Loopback)
        7. 8.3.1.7 Bias Current Generation and APC Loop
        8. 8.3.1.8 Laser Safety Features and Fault Recovery Procedure
      2. 8.3.2 Receiver
        1. 8.3.2.1 Equalizer
        2. 8.3.2.2 DC Offset Cancellation and Cross Point Control
        3. 8.3.2.3 CDR
        4. 8.3.2.4 Output Driver
        5. 8.3.2.5 Receiver Loopback (Optical Loopback)
        6. 8.3.2.6 Loss of Signal Detection
      3. 8.3.3 Analog Block
        1. 8.3.3.1 Analog Reference and Temperature Sensor
        2. 8.3.3.2 Power-On Reset
        3. 8.3.3.3 Analog to Digital Converter
        4. 8.3.3.4 2-Wire Interface and Control Logic
        5. 8.3.3.5 Bus Idle
        6. 8.3.3.6 Start Data Transfer
        7. 8.3.3.7 Stop Data Transfer
        8. 8.3.3.8 Data Transfer
      4. 8.3.4 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Differential Transmitter Output
      2. 8.4.2 Single-Ended Transmitter Output
    5. 8.5 Programming
    6. 8.6 Register Mapping
      1. 8.6.1 R/W Control Registers
        1. 8.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
        2. 8.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
        3. 8.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
        4. 8.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
      2. 8.6.2 RX Registers
        1. 8.6.2.1 RX Register 4 (offset = 0000 0000) [reset = 0h]
        2. 8.6.2.2 RX Register 5 (offset = 0000 0000) [reset = 0h]
        3. 8.6.2.3 RX Register 6 (offset = 0000 0000) [reset = 0h]
        4. 8.6.2.4 RX Register 7 (offset = 0000 0000) [reset = 0h]
        5. 8.6.2.5 RX Register 8 (offset = 0000 0000) [reset = 0h]
        6. 8.6.2.6 RX Register 9 (offset = 0000 0000) [reset = 0h]
      3. 8.6.3 TX Registers
        1. 8.6.3.1  TX Register 10 (offset = 0000 0000) [reset = 0h]
        2. 8.6.3.2  TX Register 11 (offset = 0000 0000) [reset = 0h]
        3. 8.6.3.3  TX Register 12 (offset = 0000 0000) [reset = 0h]
        4. 8.6.3.4  TX Register 13 (offset = 0h) [reset = 0]
        5. 8.6.3.5  TX Register 14 (offset = 0000 0000) [reset = 0h]
        6. 8.6.3.6  TX Register 15 (offset = 0000 0000) [reset = 0h]
        7. 8.6.3.7  TX Register 16 (offset = 0000 0000) [reset = 0h]
        8. 8.6.3.8  TX Register 17 (offset = 0000 0000) [reset = 0h]
        9. 8.6.3.9  TX Register 18 (offset = 0000 0000) [reset = 0h]
        10. 8.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
      4. 8.6.4 Reserved Registers
        1. 8.6.4.1 Reserved Registers 20-39
      5. 8.6.5 Read Only Registers
        1. 8.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
        2. 8.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
        3. 8.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]
        4. 8.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]
      6. 8.6.6 Adjustment Registers
        1. 8.6.6.1 Adjustment Registers 44-50
        2. 8.6.6.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
  9. 9 Application Information and Implementations
    1. 9.1 Application Information
    2. 9.2 Typical Application, Transmitter Differential Mode
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
      4. 9.2.4 Typical Application, Transmitter Single-Ended Mode
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

9 Application Information and Implementations

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ONET1130EC is designed to be used in conjunction with a Transmitter Optical Sub-Assembly (TOSA) and a Receiver Optical Sub-Assembly (ROSA). The ONET1130EC, TOSA, ROSA, microcontroller and power management circuitry will typically be used in an XFP or SFP+ 10 Gbps optical transceiver. Figure 68 shows the ONET1130EC in differential mode of operation modulating a differentially driven Mach Zehnder (MZ) modulator TOSA and Figure 70 and Figure 71 show the device in single-ended output mode with an Electroabsorptive Modulated Laser (EML) TOSA. Figure 70 has the photodiode cathode available and Figure 71 has the photodiode anode available.

9.2 Typical Application, Transmitter Differential Mode

ONET1130EC Apps_Circ_Diff_Mode_SLLSEJ3.gifFigure 68. Typical Application Circuit in Differential Mode

9.2.1 Design Requirements

Table 30. Design Parameters

PARAMETER VALUE
Supply voltage 2.5 V
Transmitter input voltage 100 mVpp to 1000 mVpp differential
Transmitter output voltage 1 Vpp to 3.6 Vpp differential
Receiver input voltage 6 mVpp to 800 mVpp differential
Receiver output voltage 300 mVpp to 900 mVpp differential

9.2.2 Detailed Design Procedure

In the transmitter differential mode of operation, the output driver is intended to be used with a differentially driven Mach Zehnder (MZ) modulator TOSA. On the input side, the TXIN+ and TXIN- pins are required to be AC coupled to the signal from the host system and the input voltage should be between 100 mVpp and 1000 mVpp differential. On the output side, the TXOUT+ pin is AC coupled to the modulator positive input and the TXOUT– pin is AC coupled to the modulator negative input. A bias-T from VCC to both the TXOUT+ and TXOUT– pins is required to supply sufficient headroom voltage for the output driver transistors. It is recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied to the TXOUT+ and TXOUT– pins. If the voltage on these pins drops below approximately 2.1V then the output rise and fall times can be adversely affected.

The receiver inputs, RXIN+ and RXIN–, are AC coupled to the output of ROSA and the input voltage should be between 6 mVpp and 800 mVpp differential. The receiver outputs, RXOUT+ and RXOUT–, are AC coupled to the receiver input of the host system.

9.2.3 Application Curve

ONET1130EC PG2_V2_TX_DIFF_SLLSEJ3.pngFigure 69. Differential Mode Transmitter Output Eye Diagram

9.2.4 Typical Application, Transmitter Single-Ended Mode

ONET1130EC Simp_Schem_Apps_Circ_w_PD_Cathode_SLLSEJ3.gifFigure 70. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Cathode Available
ONET1130EC Apps_Circ_w_PD_Anode_SLLSEJ3.gifFigure 71. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Anode Available

9.2.4.1 Design Requirements

Table 31. Design Parameters

PARAMETER VALUE
Supply voltage 2.5 V
Transmitter input voltage 100 mVpp to 1000 mVpp differential
Transmitter output voltage 0.5 Vpp to 2 Vpp single-ended
Receiver input voltage 6 mVpp to 800 mVpp differential
Receiver output voltage 300 mVpp to 900 mVpp differential

9.2.4.2 Detailed Design Procedure

In the transmitter single-ended mode of operation, the output driver is intended to be used with a single-ended driven Electroabsorptive Modulated Laser (EML) TOSA. On the input side, the TXIN+ and TXIN– pins are required to be AC coupled to the signal from the host system and the input voltage should be between 100mVpp and 1000mVpp differential. On the output side, it is recommended that the TXOUT+ pin is AC coupled to the modulator input and the TXOUT– pin can be left unterminated or terminated to VCC through a 50Ω resistor. A bias-T from VCC to the TXOUT+ pin is required to supply sufficient headroom voltage for the output driver transistors. It is recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied to the TXOUT+ pin. If the voltage on this pins drops below approximately 2.1V then the output rise and fall times can be adversely affected.

The receiver inputs, RXIN+ and RXIN–, are AC coupled to the output of ROSA and the input voltage should be between 6mVpp and 800mVpp differential. The receiver outputs, RXOUT+ and RXOUT–, are AC coupled to the receiver input of the host system.

9.2.4.3 Application Curves

ONET1130EC PG2_V2_TX_SE_SLLSEJ3.pngFigure 72. Single-Ended Mode Transmitter Output Eye Diagram