JAJSFG2I December   2013  – May 2018 OPA172 , OPA2172 , OPA4172

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      JFET入力の低ノイズ・アンプ
      2.      優れたTHD性能
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison
    1. 6.1 Device Comparison
    2. 6.2 Device Family Comparison
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: OPA172
    2.     Pin Functions: OPA2172 and OPA4172
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information: OPA172
    5. 8.5 Thermal Information: OPA2172
    6. 8.6 Thermal Information: OPA4172
    7. 8.7 Electrical Characteristics
    8. 8.8 Typical Characteristics: Table of Graphs
    9. 8.9 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 EMI Rejection
      2. 9.3.2 Phase-Reversal Protection
      3. 9.3.3 Capacitive Load and Stability
    4. 9.4 Device Functional Modes
      1. 9.4.1 Common-Mode Voltage Range
      2. 9.4.2 Electrical Overstress
      3. 9.4.3 Overload Recovery
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Bidirectional Current Source
      3. 10.2.3 JFET-Input Low-Noise Amplifier
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.3 JFET-Input Low-Noise Amplifier

Figure 51 shows a low-noise composite amplifier built by adding a low noise JFET pair (Q1 and Q2) as an input preamplifier for the OPA172. Transistors Q3 and Q4 form a 2-mA current sink that biases each JFET with 1 mA of drain current. Using 3.9-kΩ drain resistors produces a gain of approximately 10 in the input amplifier, making the extremely-low, broadband-noise spectral density of the JFET pair, Q1 and Q2, the dominant noise source of the amplifier. The output impedance of the input differential amplifier is large enough that a FET-input amplifier such as the OPA172 provides superior noise performance over bipolar-input amplifiers.

The gain of the composite amplifier is given by Equation 3:

Equation 3. AV = (1 + R3 / R4)

The resistances shown are standard 1% resistor values that produce a gain of approximately 100 (99.26) with 68° of phase margin. Gains less than 10 may require additional compensation methods to provide stability. Select low resistor values to minimize the resistor thermal noise contribution to the total output noise.

OPA172 OPA2172 OPA4172 ai_lownoiseamp_bos618.gifFigure 51. JFET-Input Low-Noise Amplifier