JAJSPW7B October   2023  – April 2024 OPA2323 , OPA323 , OPA4323

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Rail-to-Rail Input
      3. 7.3.3  Rail-to-Rail Output
      4. 7.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5  Capacitive Load and Stability
      6. 7.3.6  Overload Recovery
      7. 7.3.7  EMI Rejection
      8. 7.3.8  ESD and Electrical Overstress
      9. 7.3.9  Input ESD Protection
      10. 7.3.10 Shutdown Function
      11. 7.3.11 Packages with an Exposed Thermal Pad
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 OPAx323 in Low-Side, Current Sensing Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4.     Trademarks
    5. 9.4 静電気放電に関する注意事項
    6. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCK|5
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

For VS = (V+) – (V–) = 1.8V to 5.5V (±0.85V to ±2.75V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 1.8V to 5.5V  ±0.15 ±1.25 mV
VS = 1.8V to 5.5V  TA = –40°C to 125°C ±1.35
dVOS/dT Input offset voltage drift (1) VS = 1.8V to 5.5V  TA = –40°C to 125°C ±0.4 ±1.8 µV/℃
PSRR Input offset voltage versus power supply VS = 1.8V to 5.5V  ±5 ±20 µV/V
Channel separation f = 10kHz ±1 µV/V
INPUT BIAS CURRENT
IB Input bias current (1) VS = 1.8V and VS = 5V ±0.5 ±20 pA
VS = 1.8V and VS = 5V TA = –40°C to 125°C ±1600 pA
IOS Input offset current (1) VS = 1.8V and VS = 5V ±0.25 pA
VS = 1.8V and VS = 5V TA = –40°C to 125°C ±120 pA
NOISE
EN Input voltage noise f  = 0.1Hz to 10Hz   2.8 μVPP
eN Input voltage noise density f = 100Hz 24 nV/√Hz
f = 1kHz   9  
f = 10kHz   5.5  
iN Input current noise (2) f = 1 kHz   20   fA/√Hz
INPUT VOLTAGE RANGE
VI Input voltage range VS = 1.8V to 5.5V (V–) – 0.2 (V+) + 0.15 V
CMRR Common-mode rejection ratio VS = 5.5V, (V–) – 0.2V ≤ VCM ≤ (V+) + 0.10V 100 114 dB
VS = 5.5V, (V–) – 0.2V ≤ VCM ≤ (V+) + 0.15V 90 104 dB
VS = 5.5V, (V–) – 0.2V ≤ VCM ≤ (V+) + 0.15V TA = –40°C to 125°C 84 dB
VS = 1.8V, (V–) – 0.1V ≤ VCM ≤ (V+) + 0.05V 85 103 dB
VS = 1.8V, (V–) – 0.1V ≤ VCM ≤ (V+) + 0.05V TA = –40°C to 125°C 80 dB
INPUT IMPEDANCE
ZID Differential 80 || 2 GΩ || pF
ZICM Common-mode 100 || 1 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8V, (V–) + 0.1V < VO < (V+) – 0.1V, RL = 10kΩ to VS / 2 103 120 dB
VS = 1.8V, (V–) + 0.2V < VO < (V+) – 0.2V, RL = 2kΩ to VS / 2 100 115 dB
VS = 5.5V, (V–) + 0.1V < VO < (V+) – 0.1V, RL = 10kΩ to VS / 2 112 125 dB
VS = 5.5V, (V–) + 0.2V < VO < (V+) – 0.2V, RL = 2kΩ to VS / 2  108 120 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 5.5V, G = +1, RL = 10kΩ, CL = 100pF TA = 25°C 20 MHz
SR Slew rate VS = 5.5V, G = +1, VSTEP = 5V, RL = 10kΩ, CL = 100pF 33 V/μs
THD+N Total harmonic distortion + noise (3) VS = 5V, G = +1, VO = 4VP-P, f = 10kHz, RL = 600Ω to VS / 2, CL = 50pF 0.00125 %
tS Settling time To 0.1%, VS = 5.5V, VSTEP = 4V, G = +1, CL = 10pF 200 ns
To 0.1%, VS = 5.5V, VSTEP = 2V, G = +1, CL = 10pF 150
To 0.01%, VS = 5.5V, VSTEP = 4V, G = +1, CL = 10pF 250
To 0.01%, VS = 5.5V, VSTEP = 2V, G = +1, CL = 10pF 200
GM Gain Margin  VS = 5.5V, G = +1, RL = 10kΩ, CL = 30pF 15 dB
VS = 1.8V, G = +1, RL = 10kΩ, CL = 30pF 15 dB
PM Phase Margin  VS = 5.5V, G = +1, RL = 10kΩ, CL = 30pF 50 °
VS = 1.8V, G = +1, RL = 10kΩ, CL = 30pF 52.5 °
toverload Overload recovery time VIN  × gain > VS 130 ns
EMIRR Electro-magnetic interference rejection ratio f = 1.8GHz, VIN_EMIRR = 100mV 62 dB
OUTPUT
Vo Voltage output swing from rail VS = 1.8V, RL = 10kΩ to VS / 2   15 25 mV
VS = 5.5V, RL = 10kΩ to VS / 2   25 35 mV
VS = 5.5V, RL = 2kΩ to VS / 2   45 55 mV
ISC Short-circuit current (4) VS = 1.8V ±20 ±40 mA
VS = 5.5V ±80 ±110 mA
ZO Open-loop output impedance f = 10kHz 80 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 5.5V, IO = 0A 1.6 1.9 mA
TA = –40°C to 125°C 2.0
Power-on time VS = 0V to 5.5V, 90% IQ Level
 		 25 μs
SHUTDOWN
IQSD Shutdown current per amplifier (7) All amplifiers disabled, SHDN = V– 0.5 1 µA
All amplifiers disabled, SHDN = V–, TA = –40 ℃ to 125 ℃ 1.5 µA
ZSHDN Output impedance during shutdown (7) Amplifier disabled 43 || 11.5 GΩ || pF
VIH Logic high threshold voltage (amplifier enabled) (7) (V–) + 1 V V
VIL Logic low threshold voltage (amplifier disabled)  (V–) + 0.2 V V
tON Amplifier enable time (full shutdown) (5) (6) (7) G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V– 1 µs
Amplifier enable time (partial shutdown) (5) (6) (7) G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V– 1
tOFF Amplifier disable time (5) (7) G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V– 1 µs
SHDN pin input bias current (per pin) (7) (V+) ≥ SHDN ≥ (V–) + 1V 50 nA
(V–) ≤ SHDN ≤ (V–) + 0.2V 100
(1) Max or min limit is specified based on characterization results. 
(2) Typical input current noise data to be specified based on design simulation results
(3) Third-order filter; bandwidth = 80kHz at –3dB.
(4) Short circuit current specified here is average of sourcing and sinking short circuit currents
(5) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(6) Full shutdown refers to the dual device having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad device having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing circuitry remains operational and the enable time is shorter.
(7) Shutdown section is on preview