JAJS180G may   2006  – may 2023 OPA2365 , OPA365

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA365
    5. 7.5 Thermal Information: OPA2365
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input
      2. 8.3.2 Input and ESD Protection
      3. 8.3.3 Capacitive Loads
      4. 8.3.4 Achieving an Output Level of Zero Volts (0 V)
      5. 8.3.5 Active Filtering
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Amplifier Configurations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 Driving an Analog-to-Digital Converter
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 10.1.1.3 DIP アダプタ評価基板
        4. 10.1.1.4 DIYAMP-EVM
        5. 10.1.1.5 TI のリファレンス・デザイン
        6. 10.1.1.6 フィルタ設計ツール
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics

at TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 100 200 µV
dVOS/dT Input offset voltage versus drift At TA = −40°C to +125°C 1 µV/°C
PSRR Input offset voltage versus power supply VS = 2.2 V to 5.5 V,
at TA = −40°C to +125°C		 10 µV/V
Channel separation, DC 0.2 µV/V
INPUT BIAS CURRENT
IB Input bias current ±0.2 ±10 pA
Over temperature At TA = −40°C to +125°C See Section 7.7
IOS Input offset current ±0.2 ±10 pA
NOISE
en Input voltage noise f = 0.1 Hz to 10 Hz 5 µVPP
en Input voltage noise density f = 100 kHz 4.5 nV/√ Hz
in Input current noise density f = 10 kHz 4 fA/√ Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio (V−) − 0.1 V ≤ VCM ≤ (V+) + 0.1 V,
at TA = −40°C to +125°C		 100 120 dB
INPUT CAPACITANCE
Differential 6 pF
Common-mode 2 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain RL = 10 kΩ,
100 mV < VO < (V+) – 100 mV,
at TA = −40°C to +125°C		 100 120 dB
RL = 600 Ω, 200 mV < VO < (V+) – 200 mV 100 120
RL = 600 Ω,
200 mV < VO < (V+) – 200 mV,
at TA = −40°C to +125°C		 94
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 5 V 50 MHz
SR Slew rate VS = 5 V, G = 1 25 V/µs
tS Settling time 0.1% VS = 5 V, 4-V step, G = +1 200 ns
0.01% VS = 5 V, 4-V step, G = +1 300
Overload recovery time VS = 5 V, VIN × Gain > VS < 0.1 µs
THD+N Total harmonic distortion + noise(1) VS = 5 V, RL = 600 Ω, VO = 4 VPP,
G = 1, f = 1 kHz		 0.0004%
OUTPUT
Voltage output swing from rail   RL = 10 kΩ, VS = 5.5 V,
at TA = −40°C to +125°C		 10 20 mV
ISC Short-circuit current ±65 mA
CL Capacitive load drive See Section 7.7
Open-loop output impedance f = 1 MHz, IO = 0 mA 30 Ω
POWER SUPPLY
VS Specified voltage range 2.2 5.5 V
IQ Quiescent current per amplifier IO = 0 mA 4.6 5 mA
Over temperature At TA = −40°C to +125°C 5
(1) 3rd-order filter; bandwidth 80 kHz at −3 dB.