JAJSL77A February   2021  – April 2021 OPA2607-Q1 , OPA607-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
      3. 8.3.3 Input and ESD Protection
      4. 8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operating Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 100-kΩ Gain Transimpedance Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Noninverting Gain of 3 V/V
      3. 9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

Designs that require high bandwidth from a large area detector with relatively high transimpedance-gain benefit from the low input voltage noise of the OPAx607-Q1 devices. Use the Excel™ calculator available at What You Need To Know About Transimpedance Amplifiers – Part 1 to help with the component selection based on total input capacitance and CTOT. CTOT is referred as CIN in the calculator. CTOT is the sum of CD, CDIFF, and CCM which is 20 pF. Using this value of CTOT, and the targeted closed-loop bandwidth (f–3dB) of 2 MHz and transimpedance gain of 100 kΩ results in amplifier GBW of approximately 50 MHz and a feedback capacitance (CF) of 1.1 pF as shown in Figure 9-2. These results are for a Butterworth response with a Q = 0.707 and a phase margin of approximately 65° which corresponds to 4.3% overshoot.

GUID-D1D085DE-DE39-484B-848A-251B2CDF9A64-low.gifFigure 9-2 Results of Inputting Design Parameters in the TIA Calculator

The OPA607-Q1's 50 MHz GBW, is suitable for the above design requirements. If the required feedback capacitance CF comes out to be a very low value capacitor to be practically achievable, a T-Network capacitor circuit as shown below can be used. A very low capacitor value (CEQ) can be achieved between Port1 and Port2 using standard value capacitors in a T-Network circuit as shown in Figure 9-3.

Equation 1. GUID-F8FBF2C5-2959-4987-B882-3DE117258B68-low.gif

GUID-7825AA9C-1872-45BC-AEB9-1030DCA75BC4-low.gifFigure 9-3 T-Network