JAJSMI7A July   2022  – December 2022 OPA817

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Typical Characteristics: VS = ±5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 FET-Input Architecture with Wide Gain-Bandwidth Product
      4. 8.3.4 Device Functional Modes
        1. 8.3.4.1 Power-Down (PD) Pin
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Wideband, High-Input Impedance DAQ Front-End
    2. 9.2 Typical Applications
      1. 9.2.1 High Input Impedance, 200 MHz, Digitizer Front-End Amplifier Design
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.3 Detailed Design Procedure

  • Input Impedance: The JFET-input stage of the OPA817 offers giga ohm's of input impedance and therefore enables the front-end to be terminated with a 1 MΩ resistor while achieving excellent precision. A 50 Ω resistance can also be switched in offering matched termination for high-frequency signals. The OPA817 therefore enables the designer to use both 1 MΩ and 50 Ω termination in the same signal chain.
  • Noise: The total noise of the front-end amplifier is the function of the voltage and current noise of the OPA817, input termination, and the resistors thermal noise. In 50 Ω mode, the dominant noise source, however, is contributed by the voltage noise of the OPA817 due to its presence across the complete bandwidth. Thus, the total RMS noise of the front-end amplifier shall be approximately equal to the voltage noise of OPA817 over 200 MHz.

    The specified input referred voltage noise of the OPA817 is 4.5 nV/√Hz; for more information see Section 7.5. The total integrated RMS noise at the input in a bandwidth of 200 MHz is given by the following equation:

    Equation 1. EnRMS = 4.5 nV/√Hz × √ (200 MHz × 1.57) = 80 µVRMS.

    The Brickwall correction factor of 1.57 is applied assuming the bandwidth will be limited to 200 MHz with a single pole RC-filter before digitizing the signal with the ADC. Detailed calculations can be found on TI Precision Labs – Op Amps: Noise – Spectral Density.

  • Optimizing Overshoot: The OPA817 features an internal slew-boost circuit to deliver fast rise-time in applications needing high slew rates such as when configured as a transimpedance amplifier. For applications where overshoot needs to be limited, the input slew rates can be limited with introducing a series resistance (RS) as shown in Figure 9-3. The resistance RS forms a low pass filter with the input capacitance of approximately 2.6 pF at the noninverting pin of the OPA817 limiting the input slew rate to the amplifier. Figure 9-4 shows how limiting the input slew rate to the amplifier results in good overshoot performance, and Figure 9-5 shows how this achieves a small signal and large signal bandwidth of 200 MHz.