SBAS452A September   2008  – January 2016 PCM3168A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements: System Clock
    7. 8.7  Timing Requirements: Power-On Reset
    8. 8.8  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Slave Mode)
    9. 8.9  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Master Mode)
    10. 8.10 Timing Requirements: Audio Interface for DSP and TDM (Slave Mode)
    11. 8.11 Timing Requirements: Audio Interface for DSP and TDM (Master Mode)
    12. 8.12 Timing Requirements: DAC Outputs and ADC Outputs
    13. 8.13 Timing Requirements: Four-Wire Serial Control Interface
    14. 8.14 Timing Requirements: SCL and SDA Control Interface
    15. 8.15 Typical Characteristics
      1. 8.15.1 ADC Digital Filter
      2. 8.15.2 DAC Digital Filter
      3. 8.15.3 ADC Performance
      4. 8.15.4 DAC Performance
      5. 8.15.5 Output Spectrum
      6. 8.15.6 Power-Supply
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
      2. 9.3.2  Analog Outputs
      3. 9.3.3  Voltage References
      4. 9.3.4  System Clock Input
      5. 9.3.5  Sampling Mode
      6. 9.3.6  Reset Operation
      7. 9.3.7  Highpass Filter (HPF)
      8. 9.3.8  Overflow Flag
      9. 9.3.9  Zero Flag
      10. 9.3.10 Four-Wire (SPI) Serial Control
      11. 9.3.11 Control Data Word Format
      12. 9.3.12 Register Write Operation
      13. 9.3.13 Register Read Operation
      14. 9.3.14 Two-Wire (I2C) Serial Control
      15. 9.3.15 Packet Protocol
      16. 9.3.16 Write Operation
      17. 9.3.17 Read Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Mode Control
      2. 9.4.2 Hardware Control Mode Configuration
      3. 9.4.3 Audio Serial Port Operation
      4. 9.4.4 Audio Data Interface Formats and Timing
      5. 9.4.5 Synchronization With the Digital Audio System
    5. 9.5 Register Maps
      1. 9.5.1 Control Register Definitions (Software Mode Only)
      2. 9.5.2 Register Definitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Analog Input and Output
        2. 10.2.2.2 PCM Interface
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Typical Circuit Connections
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)
      2. 12.1.2  Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)
      3. 12.1.3  VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins
      4. 12.1.4  VCOMAD and VCOMDA Pins
      5. 12.1.5  VREFAD1/2 Pins
      6. 12.1.6  VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins
      7. 12.1.7  MODE Pin
      8. 12.1.8  RST Pin
      9. 12.1.9  OVF Pin
      10. 12.1.10 System Clock and Audio Interface Clocks
      11. 12.1.11 PowerPAD
      12. 12.1.12 External Mute Control
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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発注情報

9 Detailed Description

9.1 Overview

The PCM3168A device is a high-performance, multi-channel codec targeted for automotive audio applications, such as external amplifiers, as well as home multi-channel audio applications (for example, home theaters and A/V receivers). The PCM3168A device consists of six-channel analog-to-digital converters (ADCs) and eight-channel digital-to-analog converters (DACs). The ADC input is selectable between single-ended and differential inputs. The DAC output type is fixed with a differential configuration. The PCM3168A device supports 24-bit linear PCM input and output data in standard audio formats (left-justified, right-justified, and I2S), DSP and TDM formats, and various sample frequencies from 8 kHz to 192 kHz (the ADC configuration supports only up to
96 kHz). The TDM format is useful to save interface bus line numbers for multi-channel audio data communication between the codec and digital audio processor. The PCM3168A device offers three modes for device control: two-wire I2C software, four-wire SPI software, and hardware modes.

9.2 Functional Block Diagram

PCM3168A fbd_bas452.gif

9.3 Feature Description

9.3.1 Analog Inputs

The PCM3168A device includes six ADCs, each with individual pairs of differential voltage input pins, as shown in Table 1. Additionally, the PCM3168A device has the capability of single-ended inputs. The full-scale input voltage is (0.2 × VCCAD1) VRMS at the single-ended input mode and (0.4 × VCCAD1) VRMS at the differential input mode. The input mode is selected by the MODE pin in hardware control mode or by register settings in the software control mode. In single-ended mode, VINx+ pins are used and VINx– pins must be terminated with AGNDAD1/2 through a capacitor or terminated with VCOMAD.

Table 1. Pin Assignments in Differential and Single-Ended Input Modes

CHANNEL DIFFERENTIAL INPUT MODE SINGLE-ENDED INPUT MODE
1 (ADC1) VIN1+, VIN1– VIN1+
2 (ADC2) VIN2+, VIN2– VIN2+
3 (ADC3) VIN3+, VIN3– VIN3+
4 (ADC4) VIN4+, VIN4– VIN4+
5 (ADC5) VIN5+, VIN5– VIN5+
6 (ADC6) VIN6+, VIN6– VIN6+

9.3.2 Analog Outputs

The The PCM3168A device includes eight DACs, each with individual pairs of differential voltage inputs pins, as shown in Table 2. The full-scale output voltage is (1.6 × VCCDA1) VPP in differential mode. DC-coupled loads are allowed in addition to ac-coupled loads if the load resistance conforms to the specification.

Table 2. Pin Assignments for Differential Output

CHANNEL DIFFERENTIAL OUTPUT
1 (DAC1) VOUT1+, VOUT1–
2 (DAC2) VOUT2+, VOUT2–
3 (DAC3) VOUT3+, VOUT3–
4 (DAC4) VOUT4+, VOUT4–
5 (DAC5) VOUT5+, VOUT5–
6 (DAC6) VOUT6+, VOUT6–
7 (DAC7) VOUT7+, VOUT7–
8 (DAC8) VOUT8+, VOUT8–

9.3.3 Voltage References

The PCM3168A device includes two internal references for the six-channel ADCs; these references correspond to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog ground via decoupling capacitors. In addition, the PCM3168A device includes two pins for common-mode voltage output (VCOMDA for DACs and VCOMAD for ADCs). These pins should be also connected with an analog ground via decoupling capacitors. Furthermore, both common pins can be used to bias external high-impedance circuits, if they are required.

9.3.4 System Clock Input

The PCM3168A device requires an external system clock input applied at the SCKI input for ADC and DAC operation. The system clock operates at an integer multiple of the sampling frequency, or fS. The multiples supported in ADC operation include 256 fS, 384 fS, 512 fS, and 768 fS; the multiples supported in DAC operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS. Details for these system clock multiples are shown in Table 3. Figure 1 shows the SCKI timing requirements.

Table 3. System Clock Frequencies for Common Audio Sampling Rates

DEFAULT
SAMPLING
MODE
SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (MHz)
fS (kHz) 128 fS (1) 192 fS (1) 256 fS 384 fS 512 fS 768 fS
Single rate 8 N/A N/A 2.0480 3.0720(2) 4.0960 6.1440
16 2.0480(1) 3.0720(1) 4.0960 6.1440(2) 8.1920 12.2880
32 4.0960(1) 6.1440(1) 8.1920 12.2880(2) 16.3840 24.5760
44.1 5.6488(1) 8.4672(1) 11.2896 16.9344(2) 22.5792 33.8688
48 6.1440(1) 9.2160(1) 12.2880 18.4320(2) 24.5760 36.8640
Dual rate 88.2 11.2896(1) 16.9344(1) 22.5792 33.8688 N/A N/A
96 12.2880(1) 18.4320(1) 24.5760 36.8640 N/A N/A
Quad rate(1) 176.4(1) 22.5792(1) 33.8688(1) N/A N/A N/A N/A
192(1) 24.5760(1) 36.8640(1) N/A N/A N/A N/A
(1) Supported only by DAC operation
(2) Requires 50% duty cycle for stable ADC performance.

9.3.5 Sampling Mode

The PCM3168A device supports two sampling modes (single rate and dual rate) in ADC operation, and three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the ADC and DAC operate at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS). This mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the ADC and DAC operate at an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default (for example, single rate for 512 fS and 768 fS, dual rate for 256 fS and 384 fS, and quad rate for 128 fS and 192 fS), but manual selection is also possible for specified combinations through the serial mode control resistor.

Table 4 and Figure 37 show the relation between the oversampling rate (OSR) of the ΔΣ modulator, noise-free shaped bandwidth, and each sampling mode setting for ADC operation. Table 5 and Figure 38 describe the relation between the oversampling rate of the digital filter and ΔΣ modulator, noise-free shaped bandwidth, and each sampling mode setting for DAC operation.

Table 4. ADC Modulator OSR and Noise-Free Shaped Bandwidth for Each Sampling Mode

SAMPLING MODE REGISTER SETTING SYSTEM CLOCK RATE (fS) NOISE-FREE SHAPED BANDWIDTH (kHz) MODULATOR OSR
fS = 48 kHz fS = 96 kHz
Auto 512, 768 40 N/A x128
256, 384 20 40 x64
Single 512, 768 40 N/A x128
256, 384 40 N/A x128
Dual 256, 384 20 40 x64

Table 5. DAC Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth
for Each Sampling Mode

SAMPLING MODE REGISTER SETTING SYSTEM CLOCK RATE (fS) NOISE-FREE SHAPED BANDWIDTH DIGITAL FILTER OSR MODULATOR OSR
fS = 48 kHz fS = 96 kHz fS = 192 kHz
Auto 512, 768 40 N/A N/A x8 x128
256, 384 20 40 N/A x8 x64
128, 192(1)(2) 10 20 40 x4 x32
Single 512, 768 40 N/A N/A x8 x128
256, 384 40 N/A N/A x8 x128
128, 192(1)(2) 20 N/A N/A x4 x64
Dual 256, 384 20 40 N/A x8 x64
128, 192(1)(2) 20 40 N/A x4 x64
Quad 128, 192(1)(2) 10 20 40 x4 x32
(1) Supported only by DAC operation.
(2) Quad mode filter characteristic is applied.

spacer

PCM3168A ai_adc_mod_filt_char_bas452.gif Figure 37. ADC ΔΣ Modulator and Digital Filter Characteristic
PCM3168A ai_dac_mod_filt_char_bas452.gif Figure 38. DAC ΔΣ Modulator and Digital Filter Characteristic

9.3.6 Reset Operation

The PCM3168A device has both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are illustrated in Figure 2, Timing Requirements: Power-On Reset, and Figure 39. Figure 2 and Timing Requirements: Power-On Reset describe the timing chart at the internal power-on reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on if RST is kept high and SCKI is provided. VOUT from the DACs are forced to the VCOMDA level initially (0.5 × VCCDA1) and settles at a specified level according to the rising VCC. If synchronization among SCKI, BCKAD/DA, and LRCKAD/DA is maintained, VOUT starts to output with a fade-in sequence after tDACDLY1 from the internal reset release; VOUT then provides an output that corresponds to DIN after (3846 SCKI + tDACDLY1 + tDACDLY2) from power-on. Meanwhile, DOUT from the ADCs begins to output with a fade-in sequence after tADCDLY1 from the internal reset release; DOUT then provides output corresponding to VIN after (3846 SCKI + tADCDLY1 + tADCDLY2) from power-on. If the synchronization is not held, the internal reset is not released and both operating modes are maintained at reset and power-down states; after the synchronization forms again, both the DAC and ADC return to normal operation with the above sequences.

Figure 39 illustrates a timing chart at the external reset. RST accepts an external forced reset by RST = low, and provides a device reset and power-down state that makes the lowest power dissipation state available in the PCM3168A device. If RST goes from high to low under synchronization among SCKI, BCKAD/DA, and LRCKAD/DA, the internal reset is asserted, all registers and memory are reset, and finally the PCM3168A device enters into an all power-down state. At the same time, VOUT is immediately forced into the AGNDDA1 level and DOUT becomes 0. To begin normal operation again, toggle RST high; the same power-up sequence as power-on reset shown in Figure 2 is performed.

The PCM3168A device does not require particular power-on sequences for VCC and VDD; it allows VDD on and then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx and DOUTx. Figure 2 illustrates the response for VCC on with VDD on.

PCM3168A ai_tim_ex_reset_bas452.gif Figure 39. External Reset Timing Requirements

9.3.7 Highpass Filter (HPF)

The PCM3168A device includes a highpass filter (HPF) for all ADC channels in order to remove the DC component of the digitized input signal. The filter is located at the output of the digital decimation filter. The –3-dB corner frequency for the HPF scales with the output sampling rate, where f–3 dB = 0.020 × fS/1000. When
fS = 48 kHz, f–3 dB is 0.96 Hz. The HPF function can be disabled (bypassed) by the BYP bits in two channels.

9.3.8 Overflow Flag

The PCM3168A device includes an overflow flag output for all ADC channels. As soon as any of the six-channel ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. The overflow flag is held high for 1024 LRCKAD clock cycles. In parallel, overflow flag information is stored in the OVF bits of the mode control register, and the OVF bit is held until the mode control register is read. The overflow flag polarity can be changed by the OVFP bit. The OVF pin also indicates internal reset completion by transmitting a 4096 SCKI width pulse.

9.3.9 Zero Flag

The PCM3168A device includes a zero flag output for all DAC channels. When all of the eight-channel DACs digital inputs have continued as zero data for 1024 LRCKDA clock cycles, the zero flag is forced high on ZERO. In parallel, zero flag information is stored in the ZERO bits according to channel. The zero flag polarity can be changed by the ZREV bit. Also, the zero flag function can be selected by the AZRO bits. AND or OR logic for stereo, six channels, and eight channels can be selected.

9.3.10 Four-Wire (SPI) Serial Control

The PCM3168A device includes an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.

9.3.11 Control Data Word Format

All single write/read operations through the serial control port use 16-bit data words. Figure 40 shows the control data word format. The first bit is for read/write controls; 0 indicates a write operation and 1 indicates a read operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0].

PCM3168A ai_op_ctrl_mdi_bas452.gif Figure 40. Control Data Word Format for MDI

9.3.12 Register Write Operation

Figure 41 shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register must be written. To start the register write cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle has been completed, MS is set high to latch the data into the indexed mode control register.

Also, the PCM3168A device supports multiple write operations in addition to single write operations, which can be performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation can be accomplished by setting MS to a high state.

PCM3168A ai_op_reg_wr_bas452.gif
1.

NOINDENT:

X = Don't care
Figure 41. Register Write Operation

9.3.13 Register Read Operation

Figure 42 shows the functional timing diagram for single read operations on the serial control port. MS is held at a high state until a register must be read. To start the register read cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for the next write or read operation. MDO remains in a high impedance state except during the eight MC clock periods of the actual data transfer.

PCM3168A ai_op_reg_rd_bas452.gif
1.

NOINDENT:

X = Don't care
Figure 42. Register Read Operation

9.3.14 Two-Wire (I2C) Serial Control

The PCM3168A device supports an I2C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. This protocol is explained in the I2C specification, version 2.0.

The PCM3168A device has a 7-bit slave address, as shown in Figure 43. The first five bits are the most significant bits (MSB) of the slave address and are factory-preset to 10001. The next two bits of the address byte are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four PCM3168A device can be connected on the same bus at any one time. Each device responds when it receives its own slave address.

PCM3168A ai_slave_addy_bas452.gif Figure 43. Slave Address

9.3.15 Packet Protocol

A master device must control the packet protocol, which consists of the start condition, slave address with the read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop condition. The PCM3168A device supports both slave receiver and transmitter functions. Details about DATA for both write and read operations are described in Figure 44.

PCM3168A ai_tim_packet_bas452.gif
1.

NOINDENT:

R/W: Read operation if 1; write operation otherwise.
2.

NOINDENT:

ACK: Acknowledgement of a byte if 0, not Acknowledgement of a byite if 1.
3.

NOINDENT:

DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.
Figure 44. DATA Operation

9.3.16 Write Operation

The PCM3168A device supports a receiver function. A master device can write to any PCM3168A device register using single or multiple accesses. The master sends a PCM3168A device slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by one automatically. When the index register reaches 0x5E, the next value is 0x40. When undefined registers are accessed, the PCM3168A device does not send an acknowledgment. Figure 45 illustrates a diagram of the write operation. The register address and write data are in 8-bit, MSB-first format.

PCM3168A ai_op_wr_frame_bas452.gif
1.

NOINDENT:

M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.
Figure 45. Framework for Write Operation

9.3.17 Read Operation

A master device can read the registers from 0x40 to 0x5E of the PCM3168A device. The value of the register address is stored in an indirect index register in advance. The master sends the PCM3168A slave address with a read bit after storing the register address. Then the PCM3168A device transfers the data of the register with address that is in the indirect index register. Figure 46 shows a diagram of the read operation.

PCM3168A ai_op_rd_frame_bas452.gif
1.

NOINDENT:

M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge, NACK = Not acknowledge, and Sp = Stop condition.

NOINDENT:

NOTE: The slave address after the repeated start condition must be the same as the previous address.
Figure 46. Framework for Read Operation

9.4 Device Functional Modes

9.4.1 Mode Control

The PCM3168A device includes four-way mode control selectable by MODE pin, as shown in Table 6. The pull-up and pull-down resistors must be 220 kΩ ±5%. This mode control selection is sampled only when the internal reset is released by a power-on reset or by a low-to-high transition of the external reset (RST pin); a system clock is also required.

Table 6. Mode Control Selection

MODE MODE CONTROL INTERFACE
Tied to DGND Two-wire (I2C) serial control, selectable analog input configuration
Tied to DGND through pull-down resistor H/W (hardware control), differential analog input
Tied to VDD through pull-up resistor H/W (hardware control), single-ended analog input
Tied to VDD Four-wire (SPI) serial control, selectable analog input configuration

From the mode control selection described in Table 6, the functions of four pins are changed, as shown in Table 7.

Table 7. Pin Functions

PIN PIN ASSIGNMENTS
SPI I2C H/W
MS/ADR0/MD0 MS ADR0 MD0
MDO/ADR1/MD1 MDO ADR1 MD1
MDI/SDA/DEMP MDI SDA DEMP
MC/SCL/FMT MC SCL FMT

Both serial controls are available while RST = high and after internal reset completion, which is indicated as a negative transition (high ≥ low) of a 4096 × SCKI width pulse on the OVF pin.

9.4.2 Hardware Control Mode Configuration

The data format is selected by the MC/SCL/FMT pin between I2S format and I2S mode in TDM format, as shown in Table 8.

Table 8. Data Format Selection

FMT MODE CONTROL INTERFACE
Low I2S audio data format
High I2S mode, TDM audio data format (supported only for SCKI = 128 fS, 256 fS, or 512 fS)

The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in hardware control mode, as shown in Table 9. The software mode provides full selections of 32 kHz, 44.1 kHz, and 48 kHz.

Table 9. Hardware Control Mode

DEMP (DE-EMPHASIS FILTER ENABLE) DESCRIPTION
Low 44.1 kHz, de-emphasis disabled
High 44.1 kHz, de-emphasis enabled

The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The selectable multiple of the master mode audio interface is limited between 256 fS, 384 fS, and 512 fS; the selectable sampling mode is limited as shown in Table 10. The software mode provides full selections.

Table 10. Selectable Sampling Mode

MD1 MD0 DESCRIPTION
INTERFACE MODE SAMPLING MODE
ADC DAC ADC DAC
Low Low Slave(1) Slave(1) Auto(2) Auto(2)
Low High Master, 512 fS Slave(1) Single rate Auto(2)
High Low Master, 384 fS Slave(1) Dual rate Auto(2)
High High Master, 256 fS Slave(1) Dual rate Auto(2)
(1) The multiples between system clock and sampling frequency are automatically detected; 256 fS, 384 fS, 512 fS, and 768 fS are acceptable for ADC operation, and 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS are acceptable for DAC operation.
(2) The sampling mode is automatically set as single rate for 512 fS and 768 fS, dual rate for 256 fS and 384 fS, and quad rate for 128 fS and 198 fS, according to the detected multiples between the system clock and sampling clock.

9.4.3 Audio Serial Port Operation

The PCM3168A device audio serial port consists of 11 signals: BCKDA, BCKAD, LRCKDA, LRCKAD, DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, and DOUT3. The PCM3168A device also supports audio-interface mode, slave mode, and master mode. The BCKAD/DA is a bit clock input at the slave mode and an output at the master mode. The LRCKAD/DA is a left/right word clock or frame synchronization clock input at slave mode and output at master mode. The DIN1/2/3/4 are the audio data inputs for the DAC. The DOUT1/2/3 are the audio data outputs from the ADC. BCKAD, LRCKAD and DOUT1/2/3 are used for the ADC, and BCKDA, LRCKDA and DIN1/2/3/4 are used for the DAC.

9.4.4 Audio Data Interface Formats and Timing

The PCM3168A device supports eight audio data interface formats for the ADC and DAC separately in both master and slave modes: 24-bit I2S, 24-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I2S mode DSP, 24-bit left-justified mode TDM, and 24-bit I2S mode TDM format. The PCM3168A device also supports two audio data interface formats for the DAC and slave mode: 24-bit left-justified mode high-speed TDM and 24-bit I2S mode high-speed TDM format. In the case of I2S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported, but 48 BCKs are limited in slave mode and 32 BCKs are limited in slave mode 16-bit right-justified only. In the case of TDM data format in single rate, BCKAD/DA, LRCKAD/DA, DOUT1, and DIN1 are used. In the case of TDM data format in dual rate, BCKAD/DA, LRCKAD/DA, DOUT1/2, and DIN1/2 are used. In the case of high-speed TDM format in dual rate, BCKDA, LRCKDA, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCKDA, LRCKDA, and DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 fS, 256 fS, 128 fS, and fBCK ≤ fSCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode and registers 65 and 81 in software control mode. All data must be in binary twos complement, MSB first.

Figure 47 through Figure 53 show 10 audio interface data formats. Table 11 summarizes the applicable formats and describes the relationships among them and the respective restrictions with mode control.

Table 11. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions

CONTROL MODE FORMAT I/F MODE DATA BITS MAX LRCK FREQUENCY (fS) SCKI RATE (xfS) BCK RATE (xfS) APPLICABLE PINS
Software control I2S/Left-Justified Master/Slave 24 96 kHz (ADC)
192 kHz (DAC)
256 to 768 (ADC)
128 to 768 (DAC)
64, 48 (slave)(1) DOUT1/2/3
DIN1/2/3/4
Right-Justified 24, 16 64, 48 (slave)(1),
32 (slave, 16 bit)(1)
I2S/Left-Justified DSP 24 64
I2S/ Left-Justified TDM 24 48 kHz 256, 512 256 DOUT1, DIN1
24 96 kHz 128 (DAC)(2), 256 128 DOUT1/2, DIN1/2
High-Speed I2S/Left-Justified TDM Slave and DAC Only(3) 24 96 kHz 256 256 DIN1
24 192 kHz 128 128 DIN1/2
Hardware control I2S Master (ADC), Slave 24 96 kHz (ADC)
192 kHz (DAC)
256 to 768 (ADC)
128 to 768 (DAC)
64, 48 (slave)(1) DOUT1/2/3
DIN1/2/3/4
I2S TDM 24 48 kHz 512 256 DOUT1, DIN1
24 96 kHz 256 128 DOUT1/2, DIN1/2
(1) BCK = 48 fS, 32 fS is supported only in slave mode; BCK = 32 fS is supported only for 16-bit data length.
(2) SCKI = 128 fS is supported only for DAC.
(3) High-Speed I2S/Left-Justified TDM format is supported only for DAC operation in slave mode.
PCM3168A ai_tim_audio_24_i2s_bas452.gif Figure 47. Audio Data Format: 24-Bit I2S
PCM3168A ai_tim_audio_24_lj_bas452.gif Figure 48. Audio Data Format: 24-Bit Left-Justified
PCM3168A ai_tim_audio_24_rj_bas452.gif Figure 49. Audio Data Format: 24-Bit Right-Justified
PCM3168A ai_tim_audio_16_rj_bas452.gif Figure 50. Audio Data Format: 16-Bit Right-Justified
PCM3168A ai_tim_audio_24_dsp_bas452.gif Figure 51. Audio Data Format: 24-Bit DSP Format
PCM3168A ai_tim_audio_24_tdm_bas452.gif Figure 52. Audio Data Format: 24-Bit TDM Format (SCKI = 128 fS, 256 fS, and 512 fS Only)
PCM3168A ai_tim_audio_24_hs_tdm_bas452.gif Figure 53. Audio Data Format: 24-Bit High-Speed TDM Format
(SCKI = 128 fS, 256 fS, DAC, and Slave Mode Only)

9.4.5 Synchronization With the Digital Audio System

The PCM3168A device operates under the system clock (SCKI) and the audio sampling rate (LRCKAD/DA). Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode. The PCM3168A device does not need a specific phase relationship between the audio interface clocks (LRCKAD/DA, BCKAD/DA) and the system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCKAD/DA, BCKAD/DA, and SCKI.

If the relationship between SCKI and LRCKDA changes more than ±2 BCKDA clocks because of jitter, sampling frequency change, and so forth, the DAC internal operation halts within 1 / fS, and the analog output is forced into VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then tDACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than ±2 BCKADs because of jitter, sampling frequency change, and so forth, the ADC internal operation halts within 1 / fS, and the digital output is forced into a 0 code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and then tADCDLY3 passes. In the event the change is less than ±2 BCKAD/DAs, re-synchronization does not occur, and this analog/digital output control and discontinuity do not occur.

Figure 7 shows the DAC analog output and ADC digital output for loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or zero) data to normal data creates a discontinuity of data on the analog and digital outputs, which then may generate some noise in the audio signal.

Both ADC outputs (DOUTx) and DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and re-synchronization processes would occur after the system clock resumes. Figure 7 shows DAC outputs and ADC outputs for loss of synchronization.

9.5 Register Maps

Table 12. Register Map

ADDRESS DATA
DAC HEX B7 B6 B5 B4 B3 B2 B1 B0
64 40 MRST SRST SRDA1 SRDA0
65 41 PSMDA MSDA2 MSDA1 MSDA0 FMTDA3 FMTDA2 FMTDA1 FMTDA0
66 42 OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0
67 43 REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1
68 44 MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1
69 45 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1
70 46 ATMDDA ATSPDA DEMP1 DEMP0 AZRO2 AZRO1 AZRO0 ZREV
71 47 ATDA07 ATDA06 ATDA05 ATDA04 ATDA03 ATDA02 ATDA01 ATDA00
72 48 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10
73 49 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20
74 4A ATDA37 ATDA36 ATDA35 ATDA34 ATDA33 ATDA32 ATDA31 ATDA30
75 4B ATDA47 ATDA46 ATDA45 ATDA44 ATDA43 ATDA42 ATDA41 ATDA40
76 4C ATDA57 ATDA56 ATDA55 ATDA54 ATDA53 ATDA52 ATDA51 ATDA50
77 4D ATDA67 ATDA66 ATDA65 ATDA64 ATDA63 ATDA62 ATDA61 ATDA60
78 4E ATDA77 ATDA76 ATDA75 ATDA74 ATDA73 ATDA72 ATDA71 ATDA70
79 4F ATDA87 ATDA86 ATDA85 ATDA84 ATDA83 ATDA82 ATDA81 ATDA80
80 50 SRAD1 SRAD0
81 51 MSAD2 MSAD1 MSAD0 FMTAD2 FMTAD1 FMTAD0
82 52 PSVAD2 PSVAD1 PSVAD0 BYP2 BYP1 BYP0
83 53 SEAD6 SEAD5 SEAD4 SEAD3 SEAD2 SEAD1
84 54 REVAD6 REVAD5 REVAD4 REVAD3 REVAD2 REVAD1
85 55 MUTAD6 MUTAD5 MUTAD4 MUTAD3 MUTAD2 MUTAD1
86 56 OVF6 OVF5 OVF4 OVF3 OVF2 OVF1
87 57 ATMDAD ATSPAD OVFP
88 58 ATAD07 ATAD06 ATAD05 ATAD04 ATAD03 ATAD02 ATAD01 ATAD00
89 59 ATAD17 ATAD16 ATAD15 ATAD14 ATAD13 ATAD12 ATAD11 ATAD10
90 5A ATAD27 ATAD26 ATAD25 ATAD24 ATAD23 ATAD22 ATAD21 ATAD20
91 5B ATAD37 ATAD36 ATAD35 ATAD34 ATAD33 ATAD32 ATAD31 ATAD30
92 5C ATAD47 ATAD46 ATAD45 ATAD44 ATAD43 ATAD42 ATAD41 ATAD40
93 5D ATAD57 ATAD56 ATAD55 ATAD54 ATAD53 ATAD52 ATAD51 ATAD50
94 5E ATAD67 ATAD66 ATAD65 ATAD64 ATAD63 ATAD62 ATAD61 ATAD60

9.5.1 Control Register Definitions (Software Mode Only)

The PCM3168A device has many user-programmable functions that are accessed through control registers, and is programmed through the SPI or I2C serial control port. Table 13 shows the available mode control functions along with reset default conditions and associated register address. Table 12 lists the register map.

Table 13. User-Programmable Mode Control Functions

FUNCTION RESET DEFAULT REGISTER LABEL
Mode control register reset for ADC and DAC operation Normal operation 64 MRST
System reset for ADC and DAC operation Normal operation 64 SRST
DAC sampling mode selection Auto 64 SRDA[1:0]
DAC power-save mode selection Power save 65 PSMDA
DAC master/slave mode selection Slave 65 MSDA[2:0]
DAC audio interface format selection I2S 65 FMTDA[3:0]
DAC operation control Normal operation 66 OPEDA[3:0]
DAC digital filter roll-off control Sharp roll-off 66 FLT[3:0]
DAC output phase selection Normal 67 REVDA[8:1]
DAC soft mute control Mute disabled 68 MUTDA[8:1]
DAC zero flag Not detected 69 ZERO[8:1]
DAC digital attenuation mode Channel independent 70 ATMDDA
DAC digital attenuation speed N × 2048/fS 70 ATSPDA
DAC digital de-emphasis function control Disabled 70 DEMP[1:0]
DAC zero flag function selection Independent 70 AZRO[2:0]
DAC zero flag polarity selection High for detection 70 ZREV
DAC digital attenuation level shifting 0 dB, no attenuation 71–79 ATDAx[7:0]
ADC sampling mode selection Auto 80 SRAD[1:0]
ADC master/slave mode selection Slave 81 MSAD[2:0]
ADC audio interface format selection I2S 81 FMTAD[2:0]
ADC power-save control Normal operation 82 PSVAD[2:0]
ADC HPF bypass control Normal output, HPF enabled 82 BYP[2:0]
ADC input configuration control Differential 83 SEAD[6:1]
ADC input phase selection Normal 84 REVAD[6:1]
ADC soft mute control Mute disabled 85 MUTAD[6:1]
ADC overflow flag Not detected 86 OVF[6:1]
ADC digital attenuation mode Channel independent 87 ATMDAD
ADC digital attenuation speed N × 2048/fS 87 ATSPAD
ADC overflow flag polarity selection High for detection 87 OVFP
ADC digital attenuation level setting 0 dB, no gain or attenuation 88–94 ATADx[7:0]

9.5.2 Register Definitions

Table 1. Register: Reset Control

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
64 40 MRST SRST SRDA1 SRDA0
MRST Mode control register reset for the ADC and DAC
This bit sets the mode control register reset to the default value. Pop-noise may be generated. Returning the MRST bit to 1 is unneccesary, because it is automatically set to 1 after the mode control register is reset.
Default value = 1.
MRST Mode control register reset
0 Set default value
1 Normal operation (default)
SRST System reset for the ADC and DAC
This bit controls system reset, the relation between system clock and sampling clock re-synchronization, and ADC operation and DAC operation restart. The mode control register is not reset and the PCM3168A device does not go into a power-down state. The fade-in sequence is supported in the resume process, but pop-noise may be generated. Returning the SRST bit to 1 is unneccesary; it is automatically set to 1 after triggering a system reset.
Default value = 1.
SRST System reset
0 Resynchronization
1 Normal operation (default)
SRDA[1:0] DAC Sampling mode select
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is automatically set according to multiples between the system clock and sampling clock, single rate for 512 fS and 768 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA DAC Sampling mode select
00 Auto (default)
01 Single rate
10 Dual rate
11 Quad rate

Table 2. Register: DAC Control 1

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
65 41 PSMDA MSDA2 MSDA1 MSDA0 FMTDA3 FMTDA2 FMTDA1 FMTDA0
PSMDA DAC Power-save mode select
This bit selects the power-save mode for the OPEDA[3:0] function. OPEDA[3:0] is the control of power-save mode and normal operation for PSMDA = 0, or OPEDA[3:0] works as the control of DAC disable (not power-save mode) and normal operation for PSMDA = 1.
Default value: 0.
PSMDA DAC Power-save mode select
0 Power-save enable mode (default)
1 Power-save disable mode
MSDA[2:0] DAC Master/slave mode select
These bits control the audio interface mode for DAC operation.
Default value: 000 (slave mode).
MSDA DAC Master/slave mode select
000 Slave mode (default)
001 Master mode, 768 fS
010 Master mode, 512 fS
011 Master mode, 384 fS
100 Master mode, 256 fS
101 Master mode, 192 fS
110 Master mode, 128 fS
111 Reserved
FMTDA[3:0] DAC Audio interface format select
These bits control the audio interface format for DAC operation. Details of the format, and any related restrictions with the system clock and master/slave mode, are described in Audio Data Interface Formats and Timing.
Default value: 0000 (24-bit I2S format).
FMTDA DAC Audio interface format select
0000 24-bit I2S format (default)
0001 24-bit left-justified format
0010 24-bit right-justified format
0011 16-bit right-justified format
0100 24-bit I2S mode DSP format
0101 24-bit left-justified mode DSP format
0110 24-bit I2S mode TDM format
0111 24-bit left-justified mode TDM format
1000 24-bit high-speed I2S mode TDM format
1001 24-bit high-speed left-justified mode TDM format
101x Reserved
11xx Reserved

Table 3. Register: DAC Control 2

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
66 42 OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0
OPEDA[3:0] DAC Operation control
These bits control the DAC operation mode. In operation disable mode, the DAC output is cut off from DIN with a fade-out sequence, and the internal DAC data is reset. DAC output is forced into VCOMDA if PSMDA = 1, or DAC output is forced into AGNDDA and goes into a power-down state if PSMDA = 0. For normal operating mode, a fade-in sequence is applied on the DAC output in resume process. The serial mode control is effective during operation disable mode. A wait time greater than tDACDLY2 is required for the status change because of power-save control turning on/off.
Default value: 0000.
OPEDA DAC Operation control
xxx0 DAC1/2 normal operation
xxx1 DAC1/2 operation disable with or without power save
xx0x DAC3/4 normal operation
xx1x DAC3/4 operation disable with or without power save
x0xx DAC5/6 normal operation
x1xx DAC5/6 operation disable with or without power save
0xxx DAC7/8 normal operation
1xxx DAC7/8 operation disable with or without power save
FLT[3:0] DAC Digital filter roll-off control
The FLT[3:0] bits allow users to select the digital filter roll-off that is best suited to their applications. Sharp and Slow filter roll-off selections are available. The filter responses for these selections are shown in Typical Characteristics.
Default value: 0000.
FLT DAC Digital filter roll-off control
xxx0 DAC1/2 sharp roll-off
xxx1 DAC1/2 slow roll-off
xx0x DAC3/4 sharp roll-off
xx1x DAC3/4 slow roll-off
x0xx DAC5/6 sharp roll-off
x1xx DAC5/6 slow roll-off
0xxx DAC7/8 sharp roll-off
1xxx DAC7/8 slow roll-off

Table 4. Register: DAC Output Phase

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
67 43 REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1
REVDA[8:1] DAC Output phase select
The REVDA[8:1] bits are used to control the phase of DAC analog signal outputs.
Default value: 0000 0000.
REVDA DAC Output phase select3
xxxx xxx0 DAC1 normal output
xxxx xxx1 DAC1 inverted output
xxxx xx0x DAC2 normal output
xxxx xx1x DAC2 inverted output
xxxx x0xx DAC3 normal output
xxxx x1xx DAC3 inverted output
xxxx 0xxx DAC4 normal output
xxxx 1xxx DAC4 inverted output
xxx0 xxxx DAC5 normal output
xxx1 xxxx DAC5 inverted output
xx0x xxxx DAC6 normal output
xx1x xxxx DAC6 inverted output
x0xx xxxx DAC7 normal output
x1xx xxxx DAC7 inverted output
0xxx xxxx DAC8 normal output
1xxx xxxx DAC8 inverted output

Table 5. Register: DAC Soft Mute Control

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
68 44 MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1
MUTDA[8:1] DAC Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUT. The Soft Mute function is incorporated into the digital attenuators.
When Mute is disabled (MUTDA[8:1] = 0), the attenuator and DAC operate normally. When Mute is enabled by setting MUTDA[8:1] = 1, the digital attenuator for the corresponding output decreases from the current setting to infinite attenuation with an s-curve response and time set by ATSPDA.
By setting MUTDA[8:1] = 0, the attenuator increases to the last attenuation level with s-curve response in the same manner as it is for decreasing levels. This configuration provides pop and zipper noise-free muting of the DAC output.
The Soft Mute control uses the same digital attenuation level resource setting as the DAC. Mute control has priority over the digital attenuation level setting.
Default value: 0000 0000.
MUTDA DAC Soft Mute control
xxxx xxx0 DAC1 Mute disabled
xxxx xxx1 DAC1 Mute enabled
xxxx xx0x DAC2 Mute disabled
xxxx xx1x DAC2 Mute enabled
xxxx x0xx DAC3 Mute disabled
xxxx x1xx DAC3 Mute enabled
xxxx 0xxx DAC4 Mute disabled
xxxx 1xxx DAC4 Mute enabled
xxx0 xxxx DAC5 Mute disabled
xxx1 xxxx DAC5 Mute enabled
xx0x xxxx DAC6 Mute disabled
xx1x xxxx DAC6 Mute enabled
x0xx xxxx DAC7 Mute disabled
x1xx xxxx DAC7 Mute enabled
0xxx xxxx DAC8 Mute disabled
1xxx xxxx DAC8 Mute enabled

Table 6. Register: DAC Zero Flag

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
69 45 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1
ZERO[8:1] DAC Zero flag (read-only)
These bits indicate the present status of the zero detect circuit for each DAC channel; these bits are read-only.
ZERO DAC Zero flag
xxxx xxx0 DAC1 zero input not detected
xxxx xxx1 DAC1 zero input detected
xxxx xx0x DAC2 zero input not detected
xxxx xx1x DAC2 zero input detected
xxxx x0xx DAC3 zero input not detected
xxxx x1xx DAC3 zero input detected
xxxx 0xxx DAC4 zero input not detected
xxxx 1xxx DAC4 zero input detected
xxx0 xxxx DAC5 zero input not detected
xxx1 xxxx DAC5 zero input detected
xx0x xxxx DAC6 zero input not detected
xx1x xxxx DAC6 zero input detected
x0xx xxxx DAC7 zero input not detected
x1xx xxxx DAC7 zero input detected
0xxx xxxx DAC8 zero input not detected
1xxx xxxx DAC8 zero input detected

Table 7. Register: DAC Control 3

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
70 46 ATMDDA ATSPDA DEMP1 DEMP0 AZRO2 AZRO1 AZRO0 ZREV
ATMDDA DAC Attenuation mode
This bit controls the DAC attenuation mode. ATDA1[7:0] to ATDA8[7:0] are simply used for ATMDDA = 0, and ATDA0[7:0] + ATDA1[7:0] to ATDA0[7:0] + ATDA8[7:0] in decibel number are used for ATMDDA = 1.
Default value: 0.
ATMDDA DAC Attenuation mode
0 Each channel with independent data (default)
1 All channels with preset (independent) data + master (common) data in decibel number
ATSPDA DAC Attenuation speed
This bit controls the DAC attenuation speed. N × 2048/fS for ATSPDA = 0 and N × 4096/fS for ATSPDA = 1. N is automatically selected according to the DAC sampling mode, SRDA, N = 1 for single rate, N = 2 for dual rate, and N = 4 for quad rate.
Default value: 0.
ATSPDA DAC Attenuation speed
0 N × 2048/fS (default)
1 N × 4096/fS
DEMP[1:0] DAC Digital de-emphasis function/sampling rate control
These bits are used to control the enable/disable and sampling frequency of the digital de-emphasis function.
Default value: 00.
DEMP DAC Digital de-emphasis function/sampling rate control
00 Disable (default)
01 48 kHz enable
10 44.1 kHz enable
11 32 kHz enable
AZRO[2:0] DAC Zero flag function select
The AZRO[2:0] bits are used to select the function of the zero flag pin.
Default value: 000.
AZRO DAC Zero flag function select
000 DAC1/2/3/4/5/6/7/8 (8 channel) zero input detect with AND logic (default)
001 DAC1/2/3/4/5/6/7/8 (8 channel) zero input detect with OR logic
010 DAC1/2/3/4/5/6 (6 channel) zero input detect with AND logic
011 DAC1/2/3/4/5/6 (6 channel) zero input detect with OR logic
100 DAC7/8 (2 channel) zero input detect with AND logic
101 DAC7/8 (2 channel) zero input detect with OR logic
11x Reserved
ZREV DAC Zero flag polarity select
This bit controls the polarity of the zero flag pin.
Default value: 0.
ZREV DAC Zero flag polarity select
0 High for zero detect (default)
1 Low for zero detect

Table 8. Register: DAC Attenuation

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
71 47 ATDA07 ATDA06 ATDA05 ATDA04 ATDA03 ATDA02 ATDA01 ATDA00
72 48 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10
73 49 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20
74 4A ATDA37 ATDA36 ATDA35 ATDA34 ATDA33 ATDA32 ATDA31 ATDA30
75 4B ATDA47 ATDA46 ATDA45 ATDA44 ATDA43 ATDA42 ATDA41 ATDA40
76 4C ATDA57 ATDA56 ATDA55 ATDA54 ATDA53 ATDA52 ATDA51 ATDA50
77 4D ATDA67 ATDA66 ATDA65 ATDA64 ATDA63 ATDA62 ATDA61 ATDA60
78 4E ATDA77 ATDA76 ATDA75 ATDA74 ATDA73 ATDA72 ATDA71 ATDA70
79 4F ATDA87 ATDA86 ATDA85 ATDA84 ATDA83 ATDA82 ATDA81 ATDA80
ATDAx[7:0] DAC Digital attenuation level setting
Where x = 0 and 1 to 8, corresponding to the DAC channel, DACx (x = 1 to 8).
Each DAC channel (VOUTx) has a digital attenuator function. The attenuation level can be set from 0 dB to –100 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by incrementing or decrementing with s-curve responses and a time set by ATSPDA. While an attenuation level change sequence is in progress, new processing of the attenuation level change for new commands are ignored; any new commands are overwritten into the command buffer. The last command for the attenuation level change is performed after the present attenuation level change sequence is finished.
The attenuation level for each channel can be set individually using the following formula; the table below shows attenuation levels for various settings.
Attenuation level (dB) = 0.5 × (ATDAx[7:0]DEC – 255), where ATDAx[7:0]DEC = 0 through 255 for ATDAx[7:0]DEC = 0 through 54, attenuation is set to infinite attenuation (Mute).
ATDA0[7:0] are used to control all channels at the same time with attenuation data of ATDA0[7:0] + ATDAx[7:0] in decibel number, when ATMDDA is set to 1. This scheme provides preset and master volume operation.
Default value: 1111 1111.
ATDAx Decimal value Attenuation level setting
1111 1111 255 0 dB, no attenuation (default)
1111 1110 254 –0.5 dB
1111 1101 253 –1.0 dB
... ... ...
1000 0001 129 –63.0 dB
1000 0000 128 –63.5 dB
0111 1111 127 –64 dB
... ... ...
0011 1000 56 –99.5 dB
0011 0111 55 –100 dB
0011 0110 54 Mute
... ... ...
0000 0000 0 Mute

Table 9. Register: ADC Sampling Mode

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
80 50 SRAD1 SRAD0
SRAD[1:0] ADC Sampling mode select
These bits control the sampling mode of ADC operation. In Auto mode, the sampling mode is automatically set according to multiples between system clock and sampling clock, single rate for 512 fS and 768 fS, and dual rate for 256 fS and 384 fS.
Default value: 00.
SRAD ADC Sampling mode select
00 Auto (default)
01 Single rate
10 Dual rate
11 Reserved

Table 10. Register: ADC Control 1

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
81 51 MSAD2 MSAD1 MSAD0 FMTAD2 FMTAD1 FMTAD0
MSAD[2:0] ADC Master/slave mode select
These bits control the audio interface mode for ADC operation.
Default value: 000 (slave mode).
MSAD ADC Master/slave mode select
000 Slave mode (default)
001 Master mode, 768 fS
010 Master mode, 512 fS
011 Master mode, 384 fS
100 Master mode, 256 fS
101 Reserved
110 Reserved
111 Reserved
FMTAD[2:0] ADC Audio interface format select
These bits control the audio interface format for ADC operation. The format details and restrictions related to the system clock and master/slave mode are described in Audio Data Interface Formats and Timing.
Default value: 000 (24-bit I2S format).
FMTAD ADC Audio interface format select
000 24-bit I2S format (default)
001 24-bit left-justified format
010 24-bit right-justified format
011 16-bit right-justified format
100 24-bit I2S mode DSP format
101 24-bit left-justified mode DSP format
110 24-bit I2S mode TDM format
111 24-bit left-justified mode TDM format

Table 11. Register: ADC Control 2

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
82 52 PSVAD2 PSVAD1 PSVAD0 BYP2 BYP1 BYP0
PSVAD[2:0] ADC Power-save control
These bits control the ADC power-save mode. In power-save mode, DOUT is forced into ZERO with a fade-out sequence, the internal ADC data are reset, and the ADC goes into a power-down state. For power-save mode release, a fade-in sequence is applied on DOUT in resume process. The serial mode control is enabled during this mode. Wait times greater than tADCDLY2 are required for the status change because of the power-save control turning on/off.
Default value: 000.
PSVAD ADC Power-save control
xx0 ADC1/2 normal operation
xx1 ADC1/2 power-save mode
x0x ADC3/4 normal operation
x1x ADC3/4 power-save mode
0xx ADC5/6 normal operation
1xx ADC5/6 power-save mode
BYP[2:0] ADC HPF bypass control
These bits control the HPF function and dc components of the input signal; internal dc offset is converted in bypass mode.
Default value: 000.
BYP ADC HPF bypass control
xx0 ADC1/2 normal output, HPF enabled
xx1 ADC1/2 bypassed output, HPF disabled
x0x ADC3/4 normal output, HPF enabled
x1x ADC3/4 bypassed output, HPF disabled
0xx ADC5/6 normal output, HPF enabled
1xx ADC5/6 bypassed output, HPF disabled

Table 12. Register: ADC Input Configuration

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
83 53 SEAD6 SEAD5 SEAD4 SEAD3 SEAD2 SEAD1
SEAD[6:1] ADC Input configuration control
These bits control the input configuration of each ADC channel, differential or single-ended.
Default value: 00 0000 (all ADC channels have differential inputs).
SEAD ADC Input configuration
xx xxx0 ADC1 differential input
xx xxx1 ADC1 single-ended input
xx xx0x ADC2 differential input
xx xx1x ADC2 single-ended input
xx x0xx ADC3 differential input
xx x1xx ADC3 single-ended input
xx 0xxx ADC4 differential input
xx 1xxx ADC4 single-ended input
x0 xxxx ADC5 differential input
x1 xxxx ADC5 single-ended input
0x xxxx ADC6 differential input
1x xxxx ADC6 single-ended input

Table 13. Register: ADC Input Phase

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
84 54 REVAD6 REVAD5 REVAD4 REVAD3 REVAD2 REVAD1
REVAD[6:1] ADC Input phase select
These bits are used to control the phase of analog signal inputs.
Default value: 00 0000.
REVAD ADC Input phase select
xx xxx0 ADC1 normal input
xx xxx1 ADC1 inverted input
xx xx0x ADC2 normal input
xx xx1x ADC2 inverted input
xx x0xx ADC3 normal input
xx x1xx ADC3 inverted input
xx 0xxx ADC4 normal input
xx 1xxx ADC4 inverted input
x0 xxxx ADC5 normal input
x1 xxxx ADC5 inverted input
0x xxxx ADC6 normal input
1x xxxx ADC6 inverted input

Table 14. Register: ADC Soft Mute

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
85 55 MUTAD6 MUTAD5 MUTAD4 MUTAD3 MUTAD2 MUTAD1
MUTAD[6:1] ADC Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding ADC outputs, DOUT. The Soft Mute function is incorporated into the digital attenuators.
When Mute is disabled (MUTAD[6:1] = 0), the attenuator and ADC operate normally. When Mute is enabled by setting MUTAD[6:1] = 1, the digital attenuator for the corresponding output decreases from the current setting to infinite attenuation with an s-curve responses and time set by ATSPAD.
By setting MUTAD[6:1] = 0, the attenuator increases to the last attenuation level with the s-curve response in same manner as for decreasing levels. This provides pop and zipper noise-free muting for the ADC input.
The Soft Mute control uses the same digital attenuation level resource setting as the ADC. Mute control has priority over the digital attenuation level setting.
Default value: 00 0000.
MUTAD ADC Soft Mute control
xx xxx0 ADC1 Mute disabled
xx xxx1 ADC1 Mute enabled
xx xx0x ADC2 Mute disabled
xx xx1x ADC2 Mute enabled
xx x0xx ADC3 Mute disabled
xx x1xx ADC3 Mute enabled
xx 0xxx ADC4 Mute disabled
xx 1xxx ADC4 Mute enabled
x0 xxxx ADC5 Mute disabled
x1 xxxx ADC5 Mute enabled
0x xxxx ADC6 Mute disabled
1x xxxx ADC6 Mute enabled

Table 15. Register: ADC Overflow Flag

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
86 56 OVF6 OVF5 OVF4 OVF3 OVF2 OVF1
OVF[6:1] ADC Overflow flag (read-only)
These bits indicate the status information of an overflow detect circuit for each ADC channel; these bits are read only. 1 means an overflow has been detected in the past, and reading this register resets all OVF bits.
OVF ADC Overflow flag
xx xxx0 ADC1 overflow input not detected
xx xxx1 ADC1 overflow input detected
xx xx0x ADC2 overflow input not detected
xx xx1x ADC2 overflow input detected
xx x0xx ADC3 overflow input not detected
xx x1xx ADC3 overflow input detected
xx 0xxx ADC4 overflow input not detected
xx 1xx3x ADC4 overflow input detected
x0 xxxx ADC5 overflow input not detected
x1 xxxx ADC5 overflow input detected
0x xxxx ADC6 overflow input not detected
1x xxxx ADC6 overflow input detected

Table 16. Register: ADC Control 3

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
87 57 ATMDAD ATSPAD OVFP
ATMDAD ADC Attenuation mode
This bit controls the ADC attenuation mode. ATAD1[7:0] to ATAD6[7:0] are simply used for ATMDAD = 0, and ATAD0[7:0] + ATAD1[7:0] to ATAD0[7:0] + ATAD6[7:0] in decibel number are used for ATMDAD = 1.
Default value: 0.
ATMDAD ADC Attenuation mode
0 Each channel with independent data (default)
1 All channels with preset (independent) data + master (common) data in decibel number
ATSPAD ADC Attenuation speed
This bit controls the ADC attenuation Speed, N × 2048/fS for ATSPAD = 0 and N × 4096/fS for ATSPAD = 1. N is automatically selected according to the ADC sampling mode, SRAD: N = 1 for single and N = 2 for dual rate.
Default value: 0.
ATSPAD ADC Attenuation speed
0 N × 2048/fS (default)
1 N × 4096/fS
OVFP ADC Overflow flag polarity select
This bit controls the polarity of the overflow flag pin.
Default value: 0.
OVFP ADC Overflow flag polarity select
0 High for overflow detect (default)
1 Low for overflow detect

Table 17. Register: ADC Attenuation

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
88 58 ATAD07 ATAD06 ATAD05 ATAD04 ATAD03 ATAD02 ATAD01 ATAD00
89 59 ATAD17 ATAD16 ATAD15 ATAD14 ATAD13 ATAD12 ATAD11 ATAD10
90 5A ATAD27 ATAD26 ATAD25 ATAD24 ATAD23 ATAD22 ATAD21 ATAD20
91 5B ATAD37 ATAD36 ATAD35 ATAD34 ATAD33 ATAD32 ATAD31 ATAD30
92 5C ATAD47 ATAD46 ATAD45 ATAD44 ATAD43 ATAD42 ATAD41 ATAD40
93 5D ATAD57 ATAD56 ATAD55 ATAD54 ATAD53 ATAD52 ATAD51 ATAD50
94 5E ATAD67 ATAD66 ATAD65 ATAD64 ATAD63 ATAD62 ATAD61 ATAD60
ATADx[7:0] ADC Digital attenuation level setting
Where x = 0 and 1 to 6, corresponding to the ADC channel, ADCx (x = 1 to 6).
Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level can be set from 20 dB to –100 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by increment or decrement with s-curve response and time set by ATSPAD. While the attenuation level change sequence is in progress, new processing of an attenuation level change for a new command is ignored; the new command is overwritten into the command buffer. The last command for an attenuation level change is performed after the present attenuation level change sequence is finished.
The attenuation level for each channel can be set individually using the following formula, and the above table shows attenuation levels for various settings.
Attenuation level (dB) = 0.5 × (ATADx[7:0]DEC – 215), where ATADx[7:0]DEC = 0 through 255 for ATADx[7:0]DEC = 0 through 14, attenuation is set to infinite attenuation (Mute).
ATAD0[7:0] is used to control all channels at the same time with attenuation data of ATAD0[7:0] + ATADx[7:0] in decibel number, though maximum level is limited within +20 dB, when ATMDAD is set to 1. This scheme provides preset and master volume operation.
Default value: 1101 0111.
ATADx Decimal value Attenuation level setting
1111 1111 255 20.0 dB
1111 1110 254 19.5 dB
1111 1101 253 19.0 dB
... ... ...
1101 1000 216 0.5 dB
1101 0111 215 0 dB, no attenuation (default)
1101 0110 214 –0.5 dB
... ... ...
0001 0000 16 –99.5 dB
0000 1111 15 –100.0 dB
0000 1110 14 Mute
... ... ...
0000 0000 0 Mute