JAJSPR4B April   2023  – September 2023 PGA855

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 機能ブロック図
    3. 8.3 Feature Description
      1. 8.3.1 Gain Control
      2. 8.3.2 Input Protection
      3. 8.3.3 Output Common-Mode Pin
      4. 8.3.4 Using the Fully Differential Output Amplifier to Shape Noise
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Linear Operating Input Range
    2. 9.2 Typical Applications
      1. 9.2.1 ADS127L11 and ADS127L21, 24-Bit, Delta-Sigma ADC Driver Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 ADS8900B 20-Bit SAR ADC Driver Circuit
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Output Common-Mode Pin

The output voltages of the PGA855 are balanced with respect to the voltage on the output common-mode pin, VOCM. The starting point for most designs is to assign an output common-mode voltage for the PGA855. For ac-coupled signal paths, this voltage is often the default mid-supply voltage, so as to retain the most available output swing around the voltage centered at VOCM. For dc-coupled signal paths, set this voltage between a maximum of VLVDD – 1.5 V and minimum of VLVSS + 1.5 V. For precision ADC applications, this voltage is typically the input common-mode voltage of the ADC.

The voltage at the VOCM pin is internally buffered to bias the fully differential output amplifier, eliminating the need for an external VOCM buffer. In the event that the VOCM pin is left floating, the output common-mode voltage is biased at output mid-supply using an internal 500-kΩ / 500-kΩ resistor divider network connected between the output-stage power-supply pins.