SLLS888B June   2008  – October 2016 SN65HVD1050A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Electrical Characteristics: Driver
    7. 7.7  Electrical Characteristics: Receiver
    8. 7.8  Switching Characteristics: Device
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 S Pin Characteristics
    12. 7.12 VREF Pin Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant State Time-Out
      2. 9.3.2 Thermal Shutdown
      3. 9.3.3 Undervoltage Lockout and Unpowered Device
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Silent Mode
      2. 9.4.2 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Using the Device With 3.3-V Microcontrollers
      2. 10.1.2 Using SPLIT (VREF) With Split Termination
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
        3. 10.2.1.3 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ESD Protection
        2. 10.2.2.2 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
CANH 7 I/O HIGH-level CAN bus line
CANL 6 I/O LOW-level CAN bus line
GND 2 GND Ground connection
RXD 4 O CAN receiver data output (low in dominant bus state, high in recessive bus state)
VREF 5 O Common-mode stabilization output for split termination
S 8 I Silent mode select pin (active-high)
TXD 1 I CAN transmit data input (low for dominant bus state, high for recessive bus state)
VCC 3 Supply Transceiver 5-V supply voltage input