SLLSEI3A September   2013  – November 2015 SN65HVD265 , SN65HVD266 , SN65HVD267

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configurations and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: AEC
    3. 7.3 ESD Ratings: IEC
    4. 7.4 Transient Protection
    5. 7.5 Recommended Operating Conditions
    6. 7.6 Thermal Information
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant Timeout (DTO)
        1. 9.3.1.1 RXD Dominant Timeout (SN65HVD267)
        2. 9.3.1.2 Thermal Shutdown
        3. 9.3.1.3 Undervoltage Lockout
        4. 9.3.1.4 Fault Terminal (SN65HVD267)
        5. 9.3.1.5 Unpowered Device
        6. 9.3.1.6 Floating Terminals
        7. 9.3.1.7 CAN Bus Short Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Can Bus States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Silent Mode
      4. 9.4.4 Driver and Receiver Function Tables
      5. 9.4.5 Digital Inputs and Outputs
        1. 9.4.5.1 5-V VCC Only Devices (SN65HVD265 and SN65HVD267)
        2. 9.4.5.2 5-V VCC with VRXD RXD Output Supply Devices (SN65HVD266)
        3. 9.4.5.3 5-V VCC with FAULT Open-Drain Output Device (SN65HVD267)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
        2. 10.2.2.2 Functional Safety Using the SN65HVD267 in a Redundant Physical Layer CAN Network Topology
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V microprocessor applications. The bus termination is shown for illustrative purposes.

10.2 Typical Application

SN65HVD265 SN65HVD266 SN65HVD267 TypApp_Fig15_sllsei3.gif Figure 16. Typical 5-V Application

10.2.1 Design Requirements

10.2.1.1 Bus Loading, Length and Number of Nodes

The ISO11898 Standard specifies a maximum bus length of 40m and maximum stub length of 0.3m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A large number of nodes requires a transceiver with high input impedance such as the SN65HVD26x family.

Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO11898. They have made system level trade offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000.

A CAN network design is a series of tradeoffs, but these devices operate over wide common-mode range. In ISO11898-2 the driver differential output is specified with a 60Ω load (the two 120Ω termination resistors in parallel) and the differential output must be greater than 1.5V. The SN65HVD26x family is specified to meet the 1.5V requirement with a 45Ω load incorporating the worst case including parallel transceivers. The differential input resistance of the SN65HVD26x is a minimum of 30KΩ. If 167 SN65HVD26x family transceivers are in parallel on a bus, this is equivalent to a 180Ω differential load worst case. That transceiver load of 180Ω in parallel with the 60Ω gives a total 45Ω. Therefore, the SN65HVD26x family theoretically supports over 167 transceivers on a single bus segment with margin to the 1.2V minimum differential input at each node. However for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much lower. Bus length may also be extended beyond the original ISO11898 standard of 40m by careful system design and datarate tradeoffs. For example CANopen network design guidelines allow the network to be up to 1km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the responsibility of good network design and balancing these tradeoffs.

10.2.2 Detailed Design Procedures

10.2.2.1 CAN Termination

The ISO11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120 Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the cable or in a node, but if nodes may be removed from the bus the termination must be carefully placed so that it is not removed from the bus.

SN65HVD265 SN65HVD266 SN65HVD267 typ_CAN_bus_llsea2.gif Figure 17. Typical CAN Bus

Termination may be a single 120 Ω resistor at the end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used. (See Figure 18). Split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.

SN65HVD265 SN65HVD266 SN65HVD267 CAN_bus_term_llsea2.gif Figure 18. CAN Bus Termination Concepts

10.2.2.2 Functional Safety Using the SN65HVD267 in a Redundant Physical Layer CAN Network Topology

CAN is a standard linear bus topology using 120 Ω twisted pair cabling. The SN65HVD267 CAN device includes several features to use the CAN physical layer in nonstandard topologies with only one CAN link layer controller (μP) interface. This allows much greater flexibility in the physical topology of the bus while reducing the digital controller and software costs. The combination of RXD DTO and the FAULT output allows great flexibility, control and monitoring of these applications.

A simple example of this flexibility is to use two SN65HVD267 devices in parallel with an AND gate to achieve redundancy (parallel) of the physical layer (cabling and PHYs) in a CAN network.

For the CAN bit-wise arbitration to work, the RXD outputs of the transceivers must connect via AND gate logic so that a dominant bit (low) from any of the branches is received by the link layer logic (μP), and appears to the link layer and above as a single physical network. The RXD DTO feature prevents a bus stuck dominant fault in a single branch from taking down the entire network by forcing the RXD terminal for the transceivers on the branch with the fault back to the recessive after the tRXD_DTO time. The remaining branch of the network continues to function. The FAULT terminal of the transceivers on the branch with the fault indicates this via the FAULT output to their host processors, which diagnose the failure condition. Adding a logic XOR with a filter adds automatic detection for a fault where one of the 2 networks goes open (recessive) in addition to the faults detected by the SN65HVD267. The S terminal (silent mode terminal) may be used to put a branch in silent mode to check each branch for other faults. Thus it is possible to implement a robust and redundant CAN network topology in a simple and low cost manner.

These concepts can be expanded into more complicated and flexible CAN network topologies to solve various system level challenges with a networked infrastructure.

SN65HVD265 SN65HVD266 SN65HVD267 redundant_netw_257_llsei3.gif
A. CAN nodes with termination are PHY 1A, PHY 2A, PHY 1Z and PHY 2Z.
B. RXD DTO prevents a single branch-stuck-dominant condition from blocking the redundant branch via the AND logic on RXD. The transceivers signal a received bus stuck dominant fault via the FAULT terminal. The system detects which branch is stuck dominant, and issues a system warning. Other network faults on a single branch that appear as recessive (not blocking the redundant network) may be detected through a logic XOR with a filter and diagnostic routines, and using the Silent Mode of the PHYs to use only one branch at a time for transmission during diagnostic mode. This combination allows robust fault detection and recovery within single branches so that they may be repaired and again provide redundancy of the physical layer.
Figure 19. Typical Redundant Physical Layer Topology Using the SN65HVD267

10.2.3 Application Curve

SN65HVD265 SN65HVD266 SN65HVD267 Typical_CAN_Transceiver.png
Figure 20. Typical CAN Transceiver Operation Using 3.3V IO Connections