JAJSRY1F June   1998  – November 2023 SN74AHC367

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configurations and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    7. 6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
    8. 6.8 Noise Characteristics
    9. 6.9 Operating Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support (Analog)
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • N|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VIH High-level input voltage VCC = 2 V 1.5 V
VCC = 3 V 2.1
VCC = 5.5 V 3.85
VIL Low-level input voltage VCC = 2 V 0.5 V
VCC = 3 V 0.9
VCC = 5.5 V 1.65
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
IOH High-level output current VCC = 2 V –50 µA
VCC = 3.3 V ± 0.3 V –4 mA
VCC = 5 V ± 0.5 V –8
IOL Low-level output current VCC = 2 V 50 µA
VCC = 3.3 V ± 0.3 V 4 mA
VCC = 5 V ± 0.5 V 8
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 100 ns/V
VCC = 5 V ± 0.5 V 20
TA Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs.