SCES603K August   2004  – October 2014 SN74AUP1G34

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplifed Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, CL = 5 pF
    7. 7.7  Switching Characteristics, CL = 10 pF
    8. 7.8  Switching Characteristics, CL = 15 pF
    9. 7.9  Switching Characteristics, CL = 30 pF
    10. 7.10 Operating Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delays, Setup and Hold Times, and Pulse Width
    2. 8.2 Enable and Disable Times
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

This single buffer gate operates from 0.8 V to 3.6 V and performs the Boolean function Y = A in positive logic. The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back-flow through the device when it is powered. The Ioff feature also allows for live insertion.

9.2 Functional Block Diagram

ld_ces603.gif

9.3 Feature Description

  • Wide operating VCC range of 0.8 V to 3.6 V
  • 3.6-V I/O tolerant to support down translation
  • Input hysteresis allows slow input transition and better switching noise immunity at the input
  • Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
  • Low noise due to slower edge rates

9.4 Device Functional Modes

Table 1. Function Table

INPUT
A		 OUTPUT
Y
H H
L L