JAJSS12J April   2004  – April 2024 SN74AVCH8T245

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.2V
    7. 5.7  Switching Characteristics, VCCA= 1.5V ± 0.1V
    8. 5.8  Switching Characteristics, VCCA= 1.8V ± 0.15V
    9. 5.9  Switching Characteristics, VCCA= 2.5V ± 0.2V
    10. 5.10 Switching Characteristics, VCCA= 3.3V ± 0.3V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design
      2. 7.3.2 Supports High-Speed Translation
      3. 7.3.3 Partial-Power-Down Mode Operation
      4. 7.3.4 Bus-Hold Circuitry
      5. 7.3.5 VCC Isolation Feature
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGV|24
  • RHL|24
  • PW|24
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The SN74AVCH8T245 is an 8-bit, dual supply noninverting bidirectional voltage level translator. Pins A1 through A4, and the control pins (DIR and OE) are referenced to VCCA, while pins B1 through B4 are referenced to VCCB. Both the A port and B port can accept I/O voltages ranging from 1.2V to 3.6V. With OE set to low, a high on DIR allows data transmission from Port A to Port B, and a low on DIR allows data transmission from Port B to Port A. When OE is set to high, both Port A and Port B outputs are in the high-impedance state. For more information, see AVC Logic Family Technology and Application.