JAJSN44J December   1982  – October 2021 SN54HC595 , SN74HC595

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Timing Requirements

over operating free-air temperature range (unless otherwise noted)
VCCTA = 25°CSN54HC595SN74HC595UNIT
MINMAXMINMAXMINMAX
fclockClock frequency2 V64.25MHz
4.5 V312125
6 V362529
twPulse durationSRCLK or RCLK high or low2 V80120100ns
4.5 V162420
6 V142017
SRCLR low2 V80120100
4.5 V162420
6 V142017
tsuSet-up timeSER before SRCLK↑2 V100150125ns
4.5 V203025
6 V172521
SRCLK↑ before RCLK↑(1)2 V7511394
4.5 V152319
6 V131916
SRCLR low before RCLK↑2 V507565
4.5 V101513
6 V91311
SRCLR high (inactive) before SRCLK↑2 V507560
4.5 V101512
6 V91311
thHold time, SER after SRCLK↑2 V000ns
4.5 V000
6 V000
This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
GUID-BD77C365-0426-4010-9953-C771E27E89B6-low.gifFigure 6-1 Timing Diagram