JAJSRJ5 October   2023 SN74LVC2G100-Q1

ADVMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Noise Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CMOS Schmitt-Trigger Inputs
      2. 8.3.2 Balanced CMOS Push-Pull Outputs
      3. 8.3.3 Clamp Diode Structure
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
    5. 8.5 Combinatorial Logic Configurations
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Tape and Reel Information
  14. 13Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • BQB|16
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 1.8 V ± 0.15 V 120 120 120 MHz
2.5 V ± 0.2 V 150 150 150
3.3 V ± 0.3 V 150 150 150
tW Pulse duration PRE or CLR low 1.8 V ± 0.15 V 4.1 ns
2.5 ± 0.2 V 3.3
3.3 V ± 0.3 V 3.3
CLK 1.8 V ± 0.15 V 4.2 4.1
2.5 ± 0.2 V 3.3 3.3
3.3 V ± 0.3 V 3.3 3.3
tSU Setup time before CLK↑ D input pin relative to CLKx pins 1.8 V ± 0.15 V 5.8 3.6 ns
2.5 ± 0.2 V 3.2 2.3
3.3 V ± 0.3 V 2.3 2.3
DAx, DBx and DCx 1.8 V ± 0.15 V 8.8 6.6
2.5 ± 0.2 V 6.2 5.3
3.3 V ± 0.3 V 5.3 5.3
DDx   1.8 V ± 0.15 V 6.8 4.6
2.5 ± 0.2 V 4.2 3.3
3.3 V ± 0.3 V 3.3 3.3
PRE or CLR Inactive 1.8 V ± 0.15 V 5 2.7
2.5 ± 0.2 V 2.8 1.9
3.3 V ± 0.3 V 1.1 1.1
tH Hold time, data after CLK↑ D input pin relative to CLKx pins 1.8 V ± 0.15 V 6.2 1 ns
2.5 ± 0.2 V 4.4 1
3.3 ± 0.3 V 4.4 1
DAx, DBx and DCx 1.8 ± 0.15 V 9.4 1
2.5 ± 0.2 V 8.4 1
3.3 ± 0.3 V 5.4 1
DDx  1.8 V ± 0.15 V 1.7 0.7
2.5 V ± 0.2 V 1.7 0.7
3.3 V ± 0.3 V 1.7 0.7