SCES625A February   2005  – November 2015 SN74VMEH22501A-EP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Live-Insertion Specifications
    7. 7.7  Timing Requirements for UBT Transceiver (I Version)
    8. 7.8  Switching Characteristics for Bus Transceiver Function (I Version)
    9. 7.9  Switching Characteristics for Bus Transceiver Function (M Version)
    10. 7.10 Switching Characteristics for UBT Transceiver (I Version)
    11. 7.11 Switching Characteristics for UBT Transceiver (M Version)
    12. 7.12 Switching Characteristics for Bus Transceiver Function (I Version)
    13. 7.13 Switching Characteristics for UBT (I Version)
    14. 7.14 Switching Characteristics for Bus Transceiver Function (I Version)
    15. 7.15 Switching Characteristics for UBT (I Version)
    16. 7.16 Skew Characteristics for Bus Transceiver (I Version)
    17. 7.17 Skew Characteristics for Bus Transceiver (M Version)
    18. 7.18 Skew Characteristics for UBT (I Version)
    19. 7.19 Skew Characteristics for UBT (M Version)
    20. 7.20 Skew Characteristics for Bus Transceiver (I Version)
    21. 7.21 Skew Characteristics for UBT (I Version)
    22. 7.22 Skew Characteristics for Bus Transceiver (I Version)
    23. 7.23 Skew Characteristics for UBT (I Version)
    24. 7.24 Maximum Data Transfer Rates
    25. 7.25 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Distributed-Load Backplane Switching Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Functional Description for Two 1-Bit Bus Transceivers
      2. 9.3.2 Functional Description for 8-Bit UBT Transceiver
      3. 9.3.3 VMEbus Summary
    4. 9.4 Device Functional Modes
      1. 9.4.1 Direction Control Model (1-Bit Transceiver)
      2. 9.4.2 Direction Control for 8 Bit UBT
      3. 9.4.3 Latch Storage and Clock Storage
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Target applications for VME backplanes include industrial controls, telecommunications, simulation, high-energy physics, office automation, and instrumentation systems.

10.2 Typical Application

SN74VMEH22501A-EP typ_app_po_sces625.gif Figure 10. Application Schematic

10.2.1 Design Requirements

The SN74VMEH22501-EP is a combination of 8-bit universal bus transceivers (UBT) and two-bit transceivers, with split LVTTL ports for control and diagnostic monitoring purposes. For the UBTs, 3B1 to 3B8 are the VME-side I/O ports and 3A1 to 3A8 are the LVTTL-side I/O ports. For the two split LVTTL-port transceivers, 1A, 2A are the LVTTL-side input ports, 1Y, 2Y are the LVTTL-side output ports, and 1B, 2B are the VME-side I/O ports (see Figure 5). The UBTs allow transparent, latched, and flip-flop modes of data transfer. It operates at 3.3-V VCC, but can accept 5.5-V input signals at both VME and LVTTL ports. The LVTTL 3A ports and Y outputs have 26-Ω series resistors to reduce the line mismatch on the daughter-card LVTTL side. With the help of Ioff, power-up 3-state, and precharge (BIAS VCC) features, the SN74VMEH22501-EP supports live insertion.

The VME-side input port has tightly controlled input-switching thresholds of ½ VCC ±50 mV for increased noise immunity. In the VMEbus, this input threshold is a clear advantage over the normal TTL or LVTTL type inputs, where VIH(min) is 2.0 V and VIL(max) is 0.8 V. Because the input threshold follows the VCC, data transfer is more immune to the fluctuation of supply voltage, as opposed the ABTE family, where the input threshold is fixed at 1.5 V ±100 mV. To optimize performance, the SN74VMEH22501-EP has been designed into a distributed VME backplane. The OEC™ circuitry, for output edge-rate control, helps reduce reflections as well as electromagnetic interference. The OEC circuitry and high ac drive strength are instrumental in achieving the goal of incident-wave switching. The VME port can source and sink very-high transient currents, which effectively helps to overdrive the reflection on the backplane during transition.

10.2.2 Detailed Design Procedure

By simulating the performance of the device using the VME64x backplane (see Figure 6), the maximum peak current in or out of the B-port output, as the devices switch from one logic state to another, was found to be equivalent to driving the lumped load shown in Figure 11.

SN74VMEH22501A-EP equiv_ac_ces357.gif Figure 11. Equivalent AC Peak Output-Current Lumped Load

In general, the rise- and fall-time distribution is shown in Figure 12. Because VME devices were designed for use into distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and high-to-low (HL) values in the lumped load shown in the PMI (see Figure 7 and Figure 8).

SN74VMEH22501A-EP g_bars_ces357.gif Figure 12. Propagation Delay of VMEH22501 Across Different Loads

10.2.3 Application Curves

Characterization-laboratory data in Figure 13 and Figure 14 show the absolute ac peak output current, with different supply voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the devices' peak ac output drive capability.

SN74VMEH22501A-EP g_pk_iolh_ces357.gif Figure 13. Peak | IO(LH) | vs VCC
SN74VMEH22501A-EP g_pk_iohl_ces357.gif Figure 14. Peak | IO(HL) | vs VCC