11.1 SN75DP130 Power Sequencing
The following power-up and power-down sequences describe how the RSTN signal is applied to the SN75DP130. See Power Dissipation.
11.1.1 Power-Up Sequence:
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Apply Vcc with less than a 10-ms ramp time for the SN75DP130 and for the SN75DP130, apply Vddd then Vcc (both having less than 10-ms ramp time) devices. Vddd must be asserted first and stable for greater than 10 µs before Vcc is applied.
- RSTN must remain asserted until Vcc/Vddd voltage has reached minimum recommended operation for more than 100 µs.
- De-assert RSTN (Note: This RSTN is a 1.05-V interface and is internally connected to Vddd_dreg through a 150-kΩ resistor).
- Device will be available for operation approximately 400 ms after a valid reset.
11.1.2 Power-Down Sequence:
- Assert RSTN to the device.
- Remove Vcc and Vddd.