JAJST67 January   2024 TAC5112-Q1

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Timing Diagrams
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Input Channel Configurations
      4. 7.3.4 Output Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Programmable Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 ADC Signal-Chain
          1. 7.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.1.2 Programmable Channel Gain Calibration
          3. 7.3.7.1.3 Programmable Channel Phase Calibration
          4. 7.3.7.1.4 Programmable Digital High-Pass Filter
          5. 7.3.7.1.5 Programmable Digital Biquad Filters
          6. 7.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 7.3.7.1.7 Configurable Digital Decimation Filters
            1. 7.3.7.1.7.1 Linear Phase Filters
              1. 7.3.7.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
        2. 7.3.7.2 DAC Signal-Chain
          1. 7.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.2.2 Programmable Channel Gain Calibration
          3. 7.3.7.2.3 Programmable Digital High-Pass Filter
          4. 7.3.7.2.4 Programmable Digital Biquad Filters
          5. 7.3.7.2.5 Programmable Digital Mixer
          6. 7.3.7.2.6 Configurable Digital Interpolation Filters
            1. 7.3.7.2.6.1 Linear Phase Filters
              1. 7.3.7.2.6.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.2.6.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.2.6.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.2.6.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.2.6.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.2.6.1.6 Sampling Rate: 384kHz or 352.8kHz
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
  9. Register Maps
    1. 8.1 TAC5212 Registers
    2. 8.2 TAC5212 Registers
    3. 8.3 TAC5212 Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Phase-Locked Loop (PLL) and Clock Generation

The device has a smart auto-configuration block to generate all necessary internal clocks required for the ADC and DAC modulators and the digital filter engine used for signal processing. This configuration is done by monitoring the frequency of the FSYNC and BCLK signals on the audio buses.

The device supports the various data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 7-6 and Table 7-7 list the supported FSYNC and BCLK frequencies.

Table 7-6 Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC (192 kHz)FSYNC (384 kHz)FSYNC (768 kHz)
16Reserved0.2560.3840.5120.7681.5363.0726.14412.288
24Reserved0.3840.5760.7681.1522.3044.6089.21618.432
320.2560.5120.7681.0241.5363.0726.14412.28824.576
480.3840.7681.1521.5362.3044.6089.21618.432Reserved
640.5121.0241.5362.0483.0726.14412.28824.576Reserved
960.7681.5362.3043.0724.6089.21618.432ReservedReserved
1281.0242.0483.0724.0966.14412.28824.576ReservedReserved
1921.5363.0724.6086.1449.21618.432ReservedReservedReserved
2562.0484.0966.1448.19212.28824.576ReservedReservedReserved
3843.0726.1449.21612.28818.432ReservedReservedReservedReserved
5124.0968.19212.28816.38424.576ReservedReservedReservedReserved
10248.19216.38424.576ReservedReservedReservedReservedReservedReserved
204816.384ReservedReservedReservedReservedReservedReservedReservedReserved
Table 7-7 Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC (7.35 kHz)FSYNC (14.7 kHz)FSYNC (22.05 kHz)FSYNC (29.4 kHz)FSYNC (44.1 kHz)FSYNC (88.2 kHz)FSYNC (176.4 kHz)FSYNC (352.8 kHz)FSYNC (705.6 kHz)
16ReservedReserved0.35280.47040.70561.41122.82245.644811.2896
24Reserved0.35280.52920.70561.05842.11684.23368.467216.9344
32Reserved0.47040.70560.94081.41122.82245.644811.289622.5792
480.35280.70561.05841.41122.11684.23368.467216.9344Reserved
640.47040.94081.41121.88162.82245.644811.289622.5792Reserved
960.70561.41122.11682.82244.23368.467216.9344ReservedReserved
1280.94081.88162.82243.76325.644811.289622.5792ReservedReserved
1921.41122.82244.23365.64488.467216.9344ReservedReservedReserved
2561.88163.76325.64487.526411.289622.5792ReservedReservedReserved
3842.82245.64488.467211.289616.9344ReservedReservedReservedReserved
5123.76327.526411.289615.052822.5792ReservedReservedReservedReserved
10247.526415.052822.5792ReservedReservedReservedReservedReservedReserved
204815.0528ReservedReservedReservedReservedReservedReservedReservedReserved

The TAC5112-Q1 also supports non-Audio sample rates beyond those listed in prior tables. Refer to Configuring Non-Audio Sample Rates for TAC5x1x devices for more details.

The TAC5112-Q1 sample rate can be configured using registers CLK_DET0 (P0_R62) and CLK_DET1 (P0_R63) for primary and secondary ASI respectively. These registers also capture the device auto-detect result for the FSYNC frequency in auto-detection mode. The registers CLK_DET2 (P0_R64) and CLK_DET3 (P0_R65) capture the BCLK to FSYNC ratio detected by the device. If the device finds any unsupported combinations of FSYNC frequency and BCLK to FSYNC ratios, the device generates an ASI clock error interrupt and mutes all the channels accordingly.

The TAC5112-Q1 also supports enabling channels while ADC or DAC channels are already in operation. This requires a pre-configuration before power to describe the maximum number of channels that can be enabled while in operation to ensure proper clock generation and use. This can be configured by using register DYN_PUPD_CFG (P0_R119). ADC_DYN_PUPD_EN and DAC_DYN_PUPD_EN bits can be used to independently enable ADC or DAC Channels' dynamic power up. Several channels can be configured using ADC_DYN_MAXCH_SEL and DAC_DYN_MAXCH_SEL bits.

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the modulators and digital filter engine, as well as other control blocks. The device also supports an option to use BCLK, GPIOx, or the GPI1 pin (as CCLK) as the audio clock source without using the PLL to reduce power consumption. However, the ADC performance may degrade based on jitter from the external clock source, and some processing features may not be supported if the external audio clock source frequency is not high enough. Therefore, TI recommends using the PLL for high-performance applications. More details and information on how to configure and use the device in low-power mode without using the PLL are discussed in the TAC5x1x Power Consumption Matrix Across Various Usage Scenarios application report.

The device also supports an audio bus controller mode operation using the GPIOx or GPI1 pin (as CCLK) as the reference input clock source and supports various flexible options and a wide variety of system clocks. More details and information on controller mode configuration and operation are discussed in the Configuring and Operating TAC5x1x as an Audio Bus Controller application report.

The audio bus clock error detection and auto-detect feature automatically generates all internal clocks but can be disabled using the IGNORE_CLK_ERR (P0_R4_D6) and CUSTOM_CLK_CFG (P0_R50_D0) register bits, respectively. In the system, this disable feature can be used to support custom clock frequencies that are not covered by the auto-detect scheme. For such application use cases, care must be taken to ensure that the multiple clock dividers are all configured appropriately. Therefore, TI recommends using the PPC3 GUI for device configuration settings; for more details see the TAC5212EVM-PDK Evaluation module user's guide and the PurePath™ console graphical development suite.