SLASF32 December 2023 TAD5142
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DAC Performance for Line Output/Head Phone Playback | |||||||
Full Scale Output Voltage | Differential output between OUTxP and OUTxM, AVDD=3.3V | 2 | VRMS | ||||
Differential Output between OUTxP and OUTxM, AVDD=1.8V | 1 | ||||||
Single-ended Output, AVDD=3.3V | 1 | ||||||
Single-ended Output, AVDD=1.8V | 0.5 | ||||||
Pseudo Differential Output between OUTxP and OUTxM, AVDD=3.3V | 1 | ||||||
Pseudo Differential Output between OUTxP and OUTxM, AVDD=1.8V | 0.5 | ||||||
SNR | Signal-to-noise ratio, A-weighted(1)(2) | Differential Output, 0dBFS Signal, AVDD=3.3V | 106 | dB | |||
Single Ended Output, 0dBFS Signal, AVDD=3.3V | 97 | ||||||
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V | 96 | ||||||
Differential Output, 0dBFS Signal, AVDD=1.8V | 100 | ||||||
Single Ended Output, 0dBFS Signal, AVDD=1.8V | 91 | ||||||
Pseudo Differential Output, 0dBFS Signal, AVDD=1.8V | 90 | ||||||
DR | Dynamic range, A-weighted(2) | Differential Output, -60dBFS Signal, AVDD=3.3V | 106 | dB | |||
Single Ended Output, -60dBFS Signal, AVDD=3.3V | 97 | ||||||
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V | 96 | ||||||
Differential Output, -60dBFS Signal, AVDD=1.8V | 100 | ||||||
Single Ended Output, -60dBFS Signal, AVDD=1.8V | 91 | ||||||
Pseudo Differential Output, -60dBFS Signal, AVDD=1.8V | 90 | ||||||
THD+N | Total harmonic distortion(2) | –95 | dB | ||||
Head Phone Load Range | 16 | Ω | |||||
Head Phone/LO Cap Load | 0 | 100 | 550 | pF | |||
Line Out Load Range | 600 | Ω | |||||
DAC Channel OTHER PARAMETERS | |||||||
Output Offset | 0 Input, Fully Differential Output | 0.2 | mV | ||||
Output Offset | 0 Input, Pseudo Differential Output | 0.4 | mV | ||||
Output Common Mode | Common Mode Level for OUTxP and OUTxM AVDD=1.8V | 0.9 | V | ||||
Output Common Mode | Common Mode Level for OUTxP and OUTxM AVDD=3.3V | 1.66 | V | ||||
Common Mode Error | DC Error in Common Mode Voltage | ±10 | mV | ||||
Output Signal Bandwidth | 20 | kHz | |||||
Input data sample word length | Programmable | 16 | 32 | Bits | |||
Digital high-pass filter cutoff frequency | First-order IIR filter with programmable coefficients, –3-dB point (default setting) |
2 | Hz | ||||
Interchannel isolation | –134 | dB | |||||
Interchannel gain mismatch | 0.1 | dB | |||||
Interchannel phase mismatch | 1-kHz sinusoidal signal | 0.01 | Degrees | ||||
PSRR | Power-supply rejection ratio | 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain | 100 | dB | |||
Mute Attenuation | –130 | dB | |||||
Pout | Output Power Delivery | Single ended/Pseudo Differential RL=16 Ohms, THD+N<1% | 62.5 | mW | |||
DIGITAL I/O | |||||||
VIL | Low-level digital input logic voltage threshold | All digital pins, IOVDD 1.8-V operation | –0.3 | 0.35 x IOVDD | V | ||
All digital pins, IOVDD 3.3-V operation | –0.3 | 0.8 | |||||
VIH | High-level digital input logic voltage threshold | All digital pins, IOVDD 1.8-V operation | 0.65 x IOVDD | IOVDD + 0.3 | V | ||
All digital pins, IOVDD 3.3-V operation | 2 | IOVDD + 0.3 | |||||
VOL | Low-level digital output voltage | All digital pins, IOL = –2 mA, IOVDD 1.8-V operation | 0.45 | V | |||
All digital pins, IOL = –2 mA, IOVDD 3.3-V operation | 0.4 | ||||||
VOH | High-level digital output voltage | All digital pins, IOH = 2 mA, IOVDD 1.8-V operation | IOVDD – 0.45 | V | |||
All digital pins, IOH = 2 mA, IOVDD 3.3-V operation | 2.4 | ||||||
IIL | Input logic-low leakage for digital inputs | All digital pins, input = 0 V | –5 | 0.1 | 5 | µA | |
IIH | Input logic-high leakage for digital inputs | All digital pins, input = IOVDD | –5 | 0.1 | 5 | µA | |
CIN | Input capacitance for digital inputs | All digital pins | 5 | pF | |||
RPD | Pulldown resistance for digital I/O pins when asserted on | 20 | kΩ | ||||
TYPICAL SUPPLY CURRENT CONSUMPTION | |||||||
IAVDD | Current consumption in sleep mode (software shutdown mode) | All device external clocks stopped | TBD | µA | |||
IIOVDD | 1 | ||||||
IAVDD | Current consumption with DAC to HP 2-channel operation at fS 16-kHz, BCLK = 512 * fS | TBD | mA | ||||
IIOVDD | 0.2 | ||||||
IAVDD | Current consumption with DAC to HP 2-channel operation at fS 48-kHz, BCLK = 512 * fS | TBD | mA | ||||
IIOVDD | TBD |