JAJSDH3A March   2016  – July 2017 TAS5782M

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation Characteristics
    7. 7.7  MCLK Timing
    8. 7.8  Serial Audio Port Timing - Slave Mode
    9. 7.9  Serial Audio Port Timing - Master Mode
    10. 7.10 I2C Bus Timing - Standard
    11. 7.11 I2C Bus Timing - Fast
    12. 7.12 SPK_MUTE Timing
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-on-Reset (POR) Function
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port
        1. 9.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 9.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 9.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 9.3.3.4 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 9.3.3.4.1 Clock Generation using the PLL
          2. 9.3.3.4.2 PLL Calculation
            1. 9.3.3.4.2.1 Examples:
        5. 9.3.3.5 Serial Audio Port - Data Formats and Bit Depths
          1. 9.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 9.3.3.6 Input Signal Sensing (Power-Save Mode)
      4. 9.3.4 Enable Device
        1. 9.3.4.1 Example
      5. 9.3.5 Volume Control
        1. 9.3.5.1 DAC Digital Gain Control
          1. 9.3.5.1.1 Emergency Volume Ramp Down
      6. 9.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 9.3.7 Error Handling and Protection Suite
        1. 9.3.7.1 Device Overtemperature Protection
        2. 9.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 9.3.7.3 DC Offset Protection
        4. 9.3.7.4 Internal VAVDD Undervoltage-Error Protection
        5. 9.3.7.5 Internal VPVDD Undervoltage-Error Protection
        6. 9.3.7.6 Internal VPVDD Overvoltage-Error Protection
        7. 9.3.7.7 External Undervoltage-Error Protection
        8. 9.3.7.8 Internal Clock Error Notification (CLKE)
      8. 9.3.8 GPIO Port and Hardware Control Pins
      9. 9.3.9 I2C Communication Port
        1. 9.3.9.1 Slave Address
        2. 9.3.9.2 Register Address Auto-Increment Mode
        3. 9.3.9.3 Packet Protocol
        4. 9.3.9.4 Write Register
        5. 9.3.9.5 Read Register
        6. 9.3.9.6 DSP Book, Page, and Register Update
          1. 9.3.9.6.1 Book and Page Change
          2. 9.3.9.6.2 Swap Flag
          3. 9.3.9.6.3 Example Use
    4. 9.4 Device Functional Modes
      1. 9.4.1 Serial Audio Port Operating Modes
      2. 9.4.2 Communication Port Operating Modes
      3. 9.4.3 Speaker Amplifier Operating Modes
        1. 9.4.3.1 Stereo Mode
        2. 9.4.3.2 Mono Mode
        3. 9.4.3.3 Master and Slave Mode Clocking for Digital Serial Audio Port
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Component Selection Criteria
      2. 10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 10.1.3 Amplifier Output Filtering
      4. 10.1.4 Programming the TAS5782M
        1. 10.1.4.1 Resetting the TAS5782M Registers and Modules
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step One: Hardware Integration
          2. 10.2.1.2.2 Step Two: System Level Tuning
          3. 10.2.1.2.3 Step Three: Software Integration
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Mono (PBTL) Systems
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Step One: Hardware Integration
          2. 10.2.2.2.2 Step Two: System Level Tuning
          3. 10.2.2.2.3 Step Three: Software Integration
        3. 10.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 10.2.3.1 Advanced 2.1 System (Two TAS5782M devices)
        2. 10.2.3.2 Design Requirements
        3. 10.2.3.3 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 DVDD Supply
      2. 11.1.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
      1. 12.2.1 2.0 (Stereo BTL) System
      2. 12.2.2 Mono (PBTL) System
      3. 12.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
  13. 13Register Maps
    1. 13.1 Registers - Page 0
      1. 13.1.1  Register 1 (0x01)
      2. 13.1.2  Register 6 (0x06)
      3. 13.1.3  Register 7 (0x07)
      4. 13.1.4  Register 8 (0x08)
      5. 13.1.5  Register 9 (0x09)
      6. 13.1.6  Register 12 (0x0C)
      7. 13.1.7  Register 13 (0x0D)
      8. 13.1.8  Register 14 (0x0E)
      9. 13.1.9  Register 15 (0x0F)
      10. 13.1.10 Register 16 (0x10)
      11. 13.1.11 Register 17 (0x11)
      12. 13.1.12 Register 18 (0x12)
      13. 13.1.13 Register 20 (0x14)
      14. 13.1.14 Register 21 (0x15)
      15. 13.1.15 Register 22 (0x16)
      16. 13.1.16 Register 23 (0x17)
      17. 13.1.17 Register 24 (0x18)
      18. 13.1.18 Register 27 (0x1B)
      19. 13.1.19 Register 28 (0x1C)
      20. 13.1.20 Register 29 (0x1D)
      21. 13.1.21 Register 30 (0x1E)
      22. 13.1.22 Register 32 (0x20)
      23. 13.1.23 Register 33 (0x21)
      24. 13.1.24 Register 34 (0x22)
      25. 13.1.25 Register 37 (0x25)
      26. 13.1.26 Register 40 (0x28)
      27. 13.1.27 Register 41 (0x29)
      28. 13.1.28 Register 42 (0x2A)
      29. 13.1.29 Register 43 (0x2B)
      30. 13.1.30 Register 44 (0x2C)
      31. 13.1.31 Register 59 (0x3B)
      32. 13.1.32 Register 60 (0x3C)
      33. 13.1.33 Register 61 (0x3D)
      34. 13.1.34 Register 62 (0x3E)
      35. 13.1.35 Register 63 (0x3F)
      36. 13.1.36 Register 64 (0x40)
      37. 13.1.37 Register 65 (0x41)
      38. 13.1.38 Register 67 (0x43)
      39. 13.1.39 Register 68 (0x44)
      40. 13.1.40 Register 69 (0x45)
      41. 13.1.41 Register 70 (0x46)
      42. 13.1.42 Register 71 (0x47)
      43. 13.1.43 Register 72 (0x48)
      44. 13.1.44 Register 73 (0x49)
      45. 13.1.45 Register 74 (0x4A)
      46. 13.1.46 Register 75 (0x4B)
      47. 13.1.47 Register 76 (0x4C)
      48. 13.1.48 Register 78 (0x4E)
      49. 13.1.49 Register 79 (0x4F)
      50. 13.1.50 Register 83 (0x53)
      51. 13.1.51 Register 85 (0x55)
      52. 13.1.52 Register 86 (0x56)
      53. 13.1.53 Register 87 (0x57)
      54. 13.1.54 Register 88 (0x58)
      55. 13.1.55 Register 91 (0x5B)
      56. 13.1.56 Register 92 (0x5C)
      57. 13.1.57 Register 93 (0x5D)
      58. 13.1.58 Register 94 (0x5E)
      59. 13.1.59 Register 95 (0x5F)
      60. 13.1.60 Register 108 (0x6C)
      61. 13.1.61 Register 119 (0x77)
      62. 13.1.62 Register 120 (0x78)
    2. 13.2 Registers - Page 1
      1. 13.2.1 Register 1 (0x01)
      2. 13.2.2 Register 2 (0x02)
      3. 13.2.3 Register 6 (0x06)
      4. 13.2.4 Register 7 (0x07)
      5. 13.2.5 Register 9 (0x09)
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デバイスの項目表記
      2. 14.1.2 開発サポート
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 改訂履歴

Changes from * Revision (March 2017) to A Revision

  • Added missing cross references to the Quick Reference TableGo
  • Changed Changed the Volume Ramp Up/Down Step default value to 11Go
  • Changed 5th bit of the I2C Slave Address table Go
  • Added DSP Book, Page, and Register Update sectionGo
  • Deleted Page 0 Registers 0x0A, 0x50, 0x51, 0x52, and 0x54Go
  • Changed the PLLE bit type of Register 4 from R to R/WGo
  • Changed Bit configuration of Register 0x14Go
  • Changed PJDV bit in Register 21 from 5-4 to 5-0Go
  • Changed Reset value of Register 0x3D to '00110000'Go
  • Changed Bit configuration of Register 0x5DGo
  • Deleted Page 1 Registers 0x05 and 0x08Go