JAJSEB2 December   2017 TCAN4420

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 AC and DC Electrical Characteristics
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 TXD Dominant Time Out (DTO)
      2. 8.3.2 CAN Bus Short Circuit Current Limiting
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Under Voltage Lockout (UVLO) and Unpowered Device
        1. 8.3.4.1 VIO Supply PIN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Polarity Configuration
      2. 8.4.2 Normal Polarity Mode
      3. 8.4.3 Reverse Polarity Mode
      4. 8.4.4 Driver and Receiver Function
      5. 8.4.5 Floating Terminals
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length and Number of Nodes
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CAN Termination
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

8.4.4 Driver and Receiver Function

The digital logic input and output levels for these devices are TTL levels with respect to VIO for compatibility with protocol controllers having 2.8 V to 5 V logic or I/O.

Table 3 and Table 4 provide the states of the CAN driver and CAN receiver in each mode.

Table 3. Driver Function Table

DEVICE MODETXD INPUT(1)BUS OUTPUTS(2)DRIVEN BUS STATE(3)
CANHCANL
Normal L H L Dominant
H or Open Z Z Biased Recessive
Reverse L L H Dominant
H or Open Z Z Biased Recessive
(1) H = high level, L = low level
(2) H = high level, L = low level, Z = high Z receiver bias
(3) For Bus state and bias see Figure 7

Table 4. Receiver Function Table

DEVICE MODECAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL		BUS STATERXD TERMINAL(1)
Normal: VID = VCANH – VCANL
Reverse: VID = VCANL – VCANH 		VID ≥ 0.9 V Dominant L
0.5 V < VID < 0.9 V Undefined Undefined
VID ≤ 0.5 V Recessive H
(1) H = high level, L = low level