JAJSMD3L April   2000  – August 2023 THS4130 , THS4131

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Voltage
        1. 9.1.1.1 Resistor Matching
      2. 9.1.2 Driving a Capacitive Load
      3. 9.1.3 Data Converters
      4. 9.1.4 Single-Supply Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 Power-Down Mode

Power-down mode is used when power saving is required. The THS4130 power-down (PD) pin is an active low input. If left unconnected, an internal 250‑kΩ resistor to VCC+ keeps the device turned on. The threshold voltage for the power-down function is approximately 1.4 V greater than VCC–. Therefore, if the PD pin is 1.4 V greater than VCC–, then the device is active. If the PD pin is less than 1.4 V greater than VCC–, then the device is off. Pull the pin to VCC– to turn the device off. Figure 8-3 shows the simplified version of the power-down circuit. While in power-down mode, the amplifier goes into a high-impedance state. The amplifier output impedance is typically greater than 1 MΩ in power-down mode.

GUID-20211209-SS0I-5L4G-F3BK-BWLH0XTWGFKF-low.svg Figure 8-3 Simplified Power-Down Circuit

Similar to an op amp in an inverting configuration, the output impedance of an FDA is determined by the feedback network configuration. In addition, the THS4130 has an internal 10‑kΩ resistor at each output that is tied to the VCM error amplifier (see Section 8.2). The differential output impedance is equal to [(2 × RF + 2 × RG) || 20 kΩ]. Figure 8-4 shows the closed=loop output impedance of the THS4130 when in power-down.

GUID-20211214-SS0I-J0TX-T799-SQRFWCLQ4TTK-low.svg
VCC = ±5 V, gain = 1 V/V, RF = 1 kΩ, PD = VCC–
Figure 8-4 Output Impedance (in Power-Down) vs Frequency