8.2 Frequency-Response Shape Factors

Figure 1 illustrates the small-signal response shape versus gain using a fixed 402-Ω feedback resistor in the circuit of Figure 61. Being a voltage-feedback based FDA, the THS4541-Q1 shows a response shape that varies with gain setting, largely determined by the loop-gain crossover frequency and phase margin at the crossover. This loop-gain crossover frequency is where the open-loop response and the noise gain intersect (where the loop gain drops to 1). The noise gain is the inverse of the voltage divider from the outputs back to the differential inputs; use a balanced divider ratio on each feedback path. In general, the noise gain (NG) does not equal the signal gain for designs providing an input match from a source impedance. NG is given by 1 + Rf / (total impedance from the inverting summing junction to ground). Using the resistor values computed in the gain sweep of Table 6, and repeating that sweep showing the NG gives Table 1, where only the exact R solutions are shown.

NG is critically important for bandwidth and all output error terms (such as DC offset and noise). For lower-speed devices, normally only the DC noise gain is considered. However, for the THS4541-Q1, with loop gain crossover at greater than 300 MHz, the feedback network produces a parasitic pole to the differential summing junctions that causes the noise gain to increase with frequency. This pole causes a lower crossover frequency than might be expected with added phase shift around the loop. Consider the feedback network (single-ended) of Figure 65, showing a parasitic 0.2 pF on the feedback 402-Ω resistor. The 0.85-pF differential input capacitance of the THS4541-Q1 is converted to single-ended as a 1.7-pF parasitic for this single-sided analysis circuit (the Rg shown is Rg2 in Figure 61).

Figure 65. Feedback Network for the Gain of 2 Configuration Using 402 Ω and Matching to a 50-Ω Source

The response shape from Vout to Vin in Figure 65 has a pole and then a zero. To describe NG, invert the Laplace transform of Vin and Vout from Figure 65 to provide the frequency-dependent NG response of Equation 1, where a zero comes in first and then a pole.

Equation 1.

The zero location is key. Using the gain of 2 values of Figure 65, the estimated zero in the NG is 588 MHz. Limiting the parasitic capacitance at the summing junctions, either differentially or signal-ended, to a ground or power plane is critical in board layouts.

Using this feedback model, and the open-loop gain and phase data for the THS4541-Q1, allows the Aol and NG curves over frequency to be drawn, as shown in Figure 66, where the peaking in the noise gain pulls the intersection point back in frequency.

Figure 66. Aol and Noise Gain Plots for the Lower Gains of Figure 61

To assess closed-loop bandwidth and peaking, the noise-gain phase must be subtracted from the THS4541-Q1 Aol phase to obtain the total phase around the loop, as shown in Figure 67.

Figure 67. Loop-Gain Phase for the Three Lower Gains of Figure 1

From Figure 66 and Figure 67, using Table 2, tabulate the loop-gain crossover frequency and phase margin at these crossovers to explain the response shapes of Figure 1.

From these crossover (or 0-dB loop gain) frequencies, a good approximation for the resulting f_–3dB is to multiply the crossover frequencies by 1.6 when the phase margin is less than 65°. Ideally, a 65° phase margin at loop-gain crossover provides a flat Butterworth closed-loop response. The 59° phase margin for the gain of 2 setting explains the nearly flat response for this condition with 1.6 × 302 MHz = 483 MHz, estimated with f_–3dB closely matching the measured 500-MHz SSBW.

The very low phase margin in the attenuator setting at 0.1 V/V explains the highly peaked response in Figure 1. This peaking can be easily compensated, as shown in the Designing Attenuators section, using feedback capacitors and a differential capacitor across the inputs.

Considering the noise gain zero as part of the loop-gain analysis shows the importance of using relatively-low, feedback-resistor values and minimizing layout parasitic capacitance on the input pins of the THS4541-Q1 to reduce the effects of this feedback pole. The TINA model does a good job of predicting these issues (the model includes the 0.85-pF differential internal capacitance); add any estimated external parasitic capacitance on the summing junctions in simulation to predict the response shape more accurately.