JAJSFL0A June   2018  – January 2019 TLC6946 , TLC6948

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図、TLC6948で48多重化
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Pin Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Built-In 16Kb Display Memory (SRAM)
      2. 9.3.2  GCLK Dual-Edge Operation
      3. 9.3.3  Programmable Constant-Sink Channel Current
        1. 9.3.3.1 Global Brightness Control (BC)
        2. 9.3.3.2 Select RIREF for a Given BC
      4. 9.3.4  Grayscale (GS) Function (PWM Control)
      5. 9.3.5  Serial Data Interface
      6. 9.3.6  LED-Open Detection (LOD)
      7. 9.3.7  Caterpillar Removal
      8. 9.3.8  Precharge FET
      9. 9.3.9  Thermal Shutdown
      10. 9.3.10 IREF Resistor Short Protection (ISP)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operating Mode
      2. 9.4.2 Power-Save Mode (PSM)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Power Supply Voltage
        2. 10.2.2.2 Channel Current and Brightness Control
        3. 10.2.2.3 SCLK and GCLK Frequency
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.3 SCLK and GCLK Frequency

SCLK is the serial data shift-in clock signal; and GCLK is the PWM-control reference-clock signal. Equation 3 shows the minimum frequency requirement for GCLK and SCLK. See TLC6946 Technical Reference Manual for more details.

Equation 3. TLC6946 TLC6948 sclk-equ.gif

where

  • fGCLK is the minimum GCLK frequency for single-edge operating mode
  • fSCLK is the minimum SCLK frequency
  • m is the GCLK number of each sub-period, determined by the PWM mode selected
  • fVR is the visual refresh rate of the entire cascading series
  • N is the number of cascaded TLC6948 devices
  • n is the number of scan lines
  • fFPS is the frame rate