SLAS579A April   2009  – June 2015 TLV2553-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  External Reference Specifications
    7. 6.7  Operating Characteristics
    8. 6.8  Timing Requirements, VREF+ = 5 V
    9. 6.9  Timing Requirements, VREF+ = 2.5 V
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Converter Operation
        1. 8.3.1.1 Data I/O Cycle
        2. 8.3.1.2 Sampling Cycle
        3. 8.3.1.3 Conversion Cycle
      2. 8.3.2  Power Up and Initialization
      3. 8.3.3  Data Input
      4. 8.3.4  Data Input - Address/Command Bits
      5. 8.3.5  Data Output Length
      6. 8.3.6  LSB Out First
      7. 8.3.7  Bipolar Output Format
      8. 8.3.8  Reference
      9. 8.3.9  EOC Output
      10. 8.3.10 Chip-Select Input (CS)
      11. 8.3.11 Power-Down Features
      12. 8.3.12 Analog MUX
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

TLV2553-Q1 pmi_do_hz_las579.gif
Figure 25. DATA OUT to Hi-Z Voltage Waveforms
TLV2553-Q1 pmi_di_ioc_las579.gifFigure 26. DATA IN and I/O CLOCK Voltage
TLV2553-Q1 pmi_cs_ioc_las579.gif
Figure 27. CS and I/O CLOCK Voltage
Waveforms
TLV2553-Q1 pmi_ioc_do_w_las579.gifFigure 28. I/O CLOCK and DATA OUT Voltage Waveforms
TLV2553-Q1 pmi_ioc_eoc_las579.gifFigure 29. I/O CLOCK and EOC Voltage Waveforms
TLV2553-Q1 pmi_eoc_do_las579.gifFigure 30. EOC and DATA OUT Voltage Waveforms
TLV2553-Q1 pmi_cs_eoc_las579.gifFigure 31. CS and EOC Waveforms
TLV2553-Q1 pmi_ioc_do_v_las579.gifFigure 32. I/O CLOCK and DATA OUT Voltage
TLV2553-Q1 t_12tx_w_cs_las579.gifFigure 33. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
TLV2553-Q1 t_12tx_wo_cs_las579.gif

NOTE:

To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 34. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
TLV2553-Q1 t_8tx_w_cs_las579.gifFigure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
TLV2553-Q1 t_8tx_wo_cs_las579.gif

NOTE:

To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
TLV2553-Q1 t_16tx_w_cs_las579.gifFigure 37. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
TLV2553-Q1 t_16tx_wo_cs_las579.gif

NOTE:

To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 38. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First