SLOS545D November   2008  – December 2014 TLV320AIC3107

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Block Diagram
  5. 5 Revision History
  6. 6 Description (Continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Dissipation Ratings
    6. 8.6 Electrical Characteristics
    7. 8.7 Audio Data Serial Interface Timing Requirements
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right Justified Mode
        2. 10.3.2.2 Left Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 10.3.3.3 Stereo Audio DAC
          1. 10.3.3.3.1 Digital Audio Processing for Playback
          2. 10.3.3.3.2 Digital Interpolation Filter
          3. 10.3.3.3.3 Delta-Sigma Audio DAC
          4. 10.3.3.3.4 Audio DAC Digital Volume Control
          5. 10.3.3.3.5 Increasing DAC Dynamic Range
          6. 10.3.3.3.6 Analog Output Common-Mode Adjustment
          7. 10.3.3.3.7 Audio DAC Power Control
      4. 10.3.4  Audio Analog Inputs
      5. 10.3.5  Analog Line Output Drivers
      6. 10.3.6  Analog High Power Output Drivers
      7. 10.3.7  Input Impedance and VCM Control
      8. 10.3.8  General Purpose I/O
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Class-D Speaker Driver
      11. 10.3.11 Short Circuit Output Protection
      12. 10.3.12 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 Analog Input Bypass Path Functionality
        2. 10.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 10.4.1.3 Passive Analog Bypass During Powerdown
      2. 10.4.2 Digital Audio Processing For Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Mode
        1. 10.5.1.1 I2C Bus Debug in a Glitched System
        2. 10.5.1.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Control Registers
      2. 10.6.2 Output Stage Volume Controls
        1. 10.6.2.1 Page 1 / Register 10:   Left Channel Audio Effects Filter N4 Coefficient LSB Register
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

RSB Package
40-Pin WQFN With Exposed Thermal Pad
Bottom View
po_40_rsb_slos545.gif
YZF Package
42-Pin DSBGA (6 × 7)
Bottom View
po_yzf_los545.gif

Pin Functions

PIN I/O DESCRIPTION
QFN WCSP(1) NAME
1 A1 SCL I I2C serial clock
2 B1 SDA I/O I2C serial data input/output
3 A2 MICDET/LINE1LM I MIC1 or Line1 analog input (left – or multifunctional) or Microphone detect
4 A3 LINE1LP I MIC1 or Line1 analog input (left + or multifunctional)
5 B3 LINE1RP I MIC1 or Line1 analog input (R + or multifunctional)
6 A4 MIC3L/LINE1RM I MIC3 or Line1 analog input (R - or multifunctional)
7 B4 LINE2LP I MIC2 or Line2 analog input (left + or multifunctional)
8 A5 LINE2RP/LINE2LM I MIC2 or Line2 analog input (left + or right - or multifunctional)
9 A6 MIC3R/LINE2RM I MIC3 or Line2 analog input (right + or multifunctional)
10 B5 MICBIAS O Microphone bias voltage output
11 B6 AVSS_ADC G ADC analog ground supply, 0 V
12 C4 AVDD_ADC P ADC analog voltage supply, 2.7 V–3.6 V
13 C5 DRVDD P High-power output driver analog voltage supply, 2.7 V–3.6 V
14 C6 HPLOUT O High-power output driver (left +)
15 D5 HPCOM O High-power output driver (left – or multifunctional)
16 D4 DRVSS G High-power output driver analog ground supply, 0 V
17 D6 HPROUT O High-power output driver (right +)
18 E5 DRVDD P High-power output driver analog voltage supply, 2.7 V–3.6 V
19 E6 LEFT_LOP O Left line output
20 F6 RIGHT_LOP O Right line output
21 F5 AVDD_DAC P DAC analog voltage supply, 2.7 V–3.6 V
22 G6 AVSS_DAC G DAC analog ground supply, 0 V
23 F4 SPOM O Class-D (or Bypass SW, WCSP only) negative differential output
24 F2, G1, G2, G3, G5 SPVSS G Class-D ground supply, 0 V
25 G4 SPVDD P Class-D voltage supply, 2.7 V–5.5 V
26 F3 SPOP O Class-D (or Bypass SW, WCSP only) positive differential output
27 E4 SWINM I Negative Bypass Switch Input
28 — SWOUTM O Negative Bypass Switch Output, to be tied to SPOM externally
29 — SWOUTP O Positive Bypass Switch Output, to be tied to SPOP externally
30 E3 SWINP I Positive Bypass Switch Input
31 F1 RESET I Reset
32 E2 GPIO1 I/O General-purpose input/output
33 D3 DVDD P Digital core voltage supply, 1.525 V–1.95 V
34 E1 MCLK I Master clock input
35 D2 BCLK I/O Audio serial data bus bit clock (input/output)
36 D1 WCLK I/O Audio serial data bus word clock (input/output)
37 C2 DIN I Audio serial data bus data input (input)
38 C1 DOUT O Audio serial data bus data output (output)
39 C3 DVSS G Digital core / I/O ground supply, 0 V
40 B2 IOVDD P I/O voltage supply, 1.1 V–3.6 V
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