JAJSCR4B November   2016  – November 2017 TLV62568

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 100% Duty Cycle Low Dropout Operation
      3. 7.3.3 Soft Startup
      4. 7.3.4 Switch Current Limit
      5. 7.3.5 Under Voltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enabling/Disabling the Device
      2. 7.4.2 Power Good
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage(2) VIN, EN, PG –0.3 6 V
SW (DC) –0.3 VIN+0.3 V
SW (AC, less than 10 ns)(3) –3.0 9 V
FB –0.3 5.5 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions(1)

MIN TYP MAX UNIT
VIN Input voltage 2.5 5.5 V
VOUT Output voltage 0.6 VIN V
IOUT Output current 1 A
TJ Operating junction temperature –40 125 °C
ISINK_PG Sink current at PG pin 1 mA
(1) Refer to the Application and Implementation section for further information.

6.4 Thermal Information

THERMAL METRIC(1) DBV
(5 Pins)		 DDC
(6 pins)		 DRL
(6 pins)		 UNIT
RθJA Junction-to-ambient thermal resistance 191.6 121.6 149.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 141.4 69.1 45.7 °C/W
RθJB Junction-to-board thermal resistance 44.5 45.5 31.1 °C/W
ψJT Junction-to-top characterization parameter 34.5 22.3 1.3 °C/W
ψJB Junction-to-board characterization parameter 43.9 46.0 31.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VIN = 5 V, TJ = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current into VIN pin Not switching 35 uA
ISD Shutdown current into VIN pin EN = 0 V 0.1 2 µA
VUVLO Under voltage lock out VIN falling 2.3 2.45 V
Under voltage lock out hysteresis 100 mV
TJSD Thermal shutdown threshold Junction temperature rising 150 °C
Junction temperature falling 130
LOGIC INTERFACE
VIH High-level threshold at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.95 1.2 V
VIL Low-level threshold at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.4 0.85 V
tSS Soft startup time TLV62568DBV 700 µs
TLV62568DRL, TLV62568PDRL, TLV62568PDDC 900
VPG Power good threshold, TLV62568P VFB rising, referenced to VFB nominal 95%
VFB falling, referenced to VFB nominal 90%
VPG,OL Power good low-level output voltage ISINK = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5 V 0.01 µA
tPG,DLY Power good delay time VFB falling 40 µs
OUTPUT
VFB Feedback regulation voltage 0.588 0.6 0.612 V
RDS(on) High-side FET on resistance 150 mΩ
Low-side FET on resistance 100
ILIM High-side FET current limit 1.5 A
fSW Switching frequency VOUT = 1.8 V 1.5 MHz

6.6 Typical Characteristics

TLV62568 TLV62568P D001_SLVSD89_TLV62568.gif
Figure 1. Quiescent Current vs Input Voltage
TLV62568 TLV62568P D003_SLVSD89_TLV62568.gif
1.
Figure 3. FB Voltage Accuracy
TLV62568 TLV62568P D002_SLVSD89_TLV62568.gif
1.
Figure 2. Shutdown Current vs Junction Temperature