JAJSEJ8B January   2018  – November 2019 TLV6700

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
      2.      出力応答
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Inputs (INA+, INB–)
      2. 8.3.2 Outputs (OUTA, OUTB)
      3. 8.3.3 Window Comparator
      4. 8.3.4 Immunity to Input Terminal Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > UVLO)
      2. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < V(POR))
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 VPULLUP to a Voltage Other Than VDD
      2. 9.1.2 Monitoring VDD
      3. 9.1.3 Monitoring a Voltage Other Than VDD
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Resistor Divider Selection
        2. 9.2.2.2 Pullup Resistor Selection
        3. 9.2.2.3 Input Supply Capacitor
        4. 9.2.2.4 Input Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(POR) Power-on reset voltage(1) VOLmax = 0.2 V, I(OUTA/B) = 15 µA 0.8 V
VIT+ Positive-going input threshold voltage VDD = 1.8V and 18 V, TJ = 25°C 398 400 402.5 mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C 396 404
VIT– Negative-going input threshold voltage VDD = 1.8V and 18 V, TJ = 25°C 391.6 394.5 397.5 mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C 387 400
Vhys Hysteresis voltage (hys = VIT+ – VIT–) 5.5 12 mV
I(INA+) Input current (at the INA+ terminal) VDD = 1.8 V and 18 V, VI = 6.5 V –25 1 25 nA
I(INB–) Input current (at the INB– terminal) VDD = 1.8 V and 18 V, VI = 0.1 V –15 1 15 nA
VOL Low-level output voltage VDD = 1.3 V, IO = 0.4 mA 250 mV
VDD = 1.8 V, IO = 3 mA 250
VDD = 5 V, IO = 5 mA 250
Ilkg(OD) Open-drain output leakage-current VDD = 1.8 V and 18 V, VO = VDD 300 nA
VDD = 1.8 V, VO = 18 V 300
IDD Supply current VDD = 1.8 V, no load 5.5 11 µA
VDD = 5 V 6 13
VDD = 12 V 6 13
VDD = 18 V 7 13
Start-up delay(2) 150 450 µs
UVLO Undervoltage lockout(3) VDD falling 1.3 1.7 V
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state.
(3) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR).