JAJSEJ9B January   2018  – October 2018 TLV6710

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ブロック概略図
  4. 改訂履歴
  5. デバイス比較表
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Inputs (INA, INB)
      2. 8.3.2 Outputs (OUTA, OUTB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > UVLO)
      2. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 8.4.3 Power On Reset (VDD < V(POR))
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Window Comparator Considerations
      2. 9.1.2 Input and Output Configurations
      3. 9.1.3 Immunity to Input Pin Voltage Transients
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Inputs (INA, INB)

The TLV6710 combines two comparators with a precision reference voltage. Each comparator has one external input; the other input is connected to the internal reference. The rising threshold on INB and the falling threshold on INA are designed and trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy when used as a window comparator. Both comparators also have built-in hysteresis that proves immunity to noise and ensures stable operation.

The comparator inputs swings from ground to 1.7 V (7.0 V absolute maximum), regardless of the device supply voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage changes on the monitored signal.

For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA voltage drops below VIT–(INA). When the voltage exceeds VIT+(INA), OUTA goes to a high-impedance state; see Figure 1.

For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB exceeds VIT+(INB). When the voltage drops below VIT–(INB) OUTB goes to a high-impedance state; see Figure 1. Together, these two comparators form a window-detection function as described in the Window Comparator Considerations section.