JAJST97 February 2024 TMUXHS4446
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
DP0+ | 39 | HS I/O | System-side, high-speed differential positive signal for DisplayPort DP0 |
DP0– | 40 | HS I/O | System-side, high-speed differential negative signal for DisplayPort DP0 |
DP1+ | 2 | HS I/O | System-side, high-speed differential positive signal for DisplayPort DP1 |
DP1– | 3 | HS I/O | System-side, high-speed differential negative signal for DisplayPort DP1 |
DP2+ | 5 | HS I/O | System-side, high-speed differential positive signal for DisplayPort DP2 |
DP2– | 6 | HS I/O | System-side, high-speed differential negative signal for DisplayPort DP2 |
DP3+ | 8 | HS I/O | System-side, high-speed differential positive signal for DisplayPort DP3 |
DP3– | 9 | HS I/O | System-side, high-speed differential negative signal for DisplayPort DP3 |
SSTX+ | 11 | HS I/O | System-side, high-speed differential positive signal for USB TX pins |
SSTX– | 12 | HS I/O | System-side, high-speed differential negative signal for USB TX pins |
SSRX+ | 16 | HS I/O | System-side, high-speed differential positive signal for USB RX pins |
SSRX– | 17 | HS I/O | System-side, high-speed differential negative signal for USB RX pins |
CRX1– | 24 | HS I/O | Connector-side, high-speed differential negative signal for USB-C RX pins |
CRX1+ | 25 | HS I/O | Connector-side, high-speed differential positive signal for USB-C RX pins |
CTX1– | 27 | HS I/O | Connector-side, high-speed differential negative signal for USB-C TX pins |
CTX1+ | 28 | HS I/O | Connector-side, high-speed differential positive signal for USB-C TX pins |
CTX2– | 30 | HS I/O | Connector-side, high-speed differential negative signal for USB-C TX pins |
CTX2+ | 31 | HS I/O | Connector-side, high-speed differential positive signal for USB-C TX pins |
CRX2- | 33 | HS I/O | Connector-side, high-speed differential negative signal for USB-C RX pins |
CRX2+ | 34 | HS I/O | Connector-side, high-speed differential positive signal for USB-C RX pins |
AUX+ | 19 | LS I/O | System-side, low-speed SBU signal for USB-C SBU pin |
AUX– | 20 | LS I/O | System-side, low-speed SBU signal for USB-C SBU pin |
SBU1 | 22 | LS I/O | Connector-side, low-speed SBU signal for USB-C SBU1 pin |
SBU2 | 21 | LS I/O | Connector-side, low-speed SBU signal for USB-C SBU2 pin |
MODE0 | 1 | CTRL | Control mode selection MODE0 = 1, I2C control MODE0 = 0, GPIO or pin control through CONF[2:0] |
MODE1 | 13 | CTRL | I2C logic level control (MODE0 = 1) MODE1 = 0, 1.8V I2C logic level MODE1 = 1, 3.3V I2C logic level |
CONF0 | 35 | CTRL | GPIO control (MODE0 = 0) Switch configuration control for high-speed and low-speed pins. Refer to the Device Functional Modes section for details. |
A1 | CTRL | I2C control (MODE0 = 1) Configurable I2C target address bit |
|
CONF1 | 36 | CTRL | GPIO control (MODE0 = 0) Switch configuration control for high-speed and low-speed pins. Refer to the Device Functional Modes section for details. |
SCL | CTRL | I2C control (MODE0 = 1) I2C clock input |
|
CONF2 | 38 | CTRL | GPIO control (MODE0 = 0) Switch configuration control for high-speed and low-speed pins. Refer to the Device Functional Modes section for details. |
SDA | CTRL | I2C control (MODE0 = 1) I2C data input |
|
A0 | 14 | CTRL | I2C control (MODE0 = 1) Configurable I2C target address bit |
VCC | 4, 7, 10, 23, 26, 29, 32 | P | Power |
GND | 15, 18, 37, Thermal Pad | G | Ground |