JAJSDX9C June   2017  – November 2018 TPS2373

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  PG Power Good (Converter Enable) Pin Interface
      3. 7.3.3  CLSA and CLSB Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  TPH, TPL and BT PSE Type Indicators
      7. 7.3.7  VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Startup
      8. 7.3.8  AMPS_CTL, MPS_DUTY and Automatic MPS
      9. 7.3.9  VDD Supply Voltage
      10. 7.3.10 VSS
      11. 7.3.11 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Startup
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Advanced Startup and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Startup and Power Management, PG and TPH, TPL, BT
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  APD Pin Divider Network RAPD1, RAPD2
        7. 8.2.2.7  Opto-isolators for TPH, TPL and BT
        8. 8.2.2.8  VC Input and Output, CVCIN and CVCOUT
        9. 8.2.2.9  UVLO Select, UVLO_SEL
        10. 8.2.2.10 Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        11. 8.2.2.11 Internal Voltage Reference, RREF
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

CLSA and CLSB Classification

Each of the two external resistors (RCLSA and RCLSB in Figure 30) connected between the CLSA (first and second class event) and CLSB (third and any subsequent class event) pins and VSS provide a distinct classification signature to the PSE, and are used to define the power class requested by the PD. The controller places a voltage of approximately 2.5 V across CLSA (first or second class event) or CLSB (all additional class events) external resistor whenever the voltage differential between VDD and VSS lies from about 10.9 V to 22 V. The current drawn by each resistor, combined with the internal current drain of the controller and any leakage through the internal pass MOSFET, creates the classification signature current. Table 1 lists the external resistor values required for each of the PD power ranges defined by IEEE802.3bt. The number of classification cycles then determines how much power is allocated by the PSE. The maximum average power drawn by the PD, plus the power supplied to the downstream load, should not exceed the maximum power indicated in Table 1, as well as the maximum power allocated by the PSE based on the number of classification cycles. Holding APD high disables the classification signatures.

Type 2 and Type 3 PSEs may perform two classification cycles if Class 4 signature is presented on the first cycle. Likewise, Type 3 and Type 4 PSEs may perform four classification cycles if Class 4 signature is presented on the first two cycles and Class 0 or 1 signature is presented on the third cycle. Also, Type 4 PSEs may perform five classification cycles if Class 4 signature is presented on the first two cycles and Class 2 or 3 signature is presented on the third cycle.

Table 1. Class Resistor Selection

PD Class CLASS SIGNATURE A CLASS SIGNATURE B MINIMUM POWER AT PD (W) MAXIMUM POWER AT PD (W) NUMBER OF CLASS CYCLES @ MAX POWER RESISTOR CLSA (Ω) RESISTOR CLSB (Ω)
0 0 0 0.44 12.95 1 1210 1210
1 1 1 0.44 3.84 1 249 249
2 2 2 3.84 6.49 1 140 140
3 3 3 6.49 12.95 1 90.9 90.9
4 4 4 12.95 25.5 2,3 63.4 63.4
5 4 0 25.5 40 4 63.4 1210
6 4 1 40 51 4 63.4 249
7 4 2 51 62 5 63.4 140
8 4 3 62 71 5 63.4 90.9