JAJSK02 October   2020 TPS23731

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     14
    8. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLS Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  Internal Pass MOSFET
      5. 8.3.5  T2P and APDO Indicators
      6. 8.3.6  DC-DC Controller Features
        1. 8.3.6.1 VCC, VB, VBG and Advanced PWM Startup
        2.       27
        3. 8.3.6.2 CS, Current Slope Compensation and blanking
        4. 8.3.6.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.6.4 FRS Frequency Setting and Synchronization
        6. 8.3.6.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.6.6 SST and Soft-Start of the Switcher
        8. 8.3.6.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      7. 8.3.7  Switching FET Driver - GATE
      8. 8.3.8  EMPS and Automatic MPS
      9. 8.3.9  VDD Supply Voltage
      10. 8.3.10 RTN, AGND, GND
      11. 8.3.11 VSS
      12. 8.3.12 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLS.
          6. 9.2.1.1.6  APD Pin Divider Network, RAPD1, RAPD2
          7. 9.2.1.1.7  Setting Frequency (RFRS) and Synchronization
          8. 9.2.1.1.8  Bias Supply Requirements and CVCC
          9. 9.2.1.1.9  APDO, T2P Interface
          10. 9.2.1.1.10 Output Voltage Feedback Divider, RAUX, R1,R2
          11. 9.2.1.1.11 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Advanced Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges CBULK, CVCC, CVB and CVBG while the PD is unpowered. Thus VVDD-RTN will be a small voltage until just after full voltage is applied to the PD, as seen in Figure 8-7.

The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon threshold (VUVLO-R, approximately 37.6 V) with RTN high, the TPS23731 enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-9 for an example. Converter switching is disabled while CBULK charges and VRTN falls from VVDD to nearly VVSS; however, the converter start-up circuit is allowed to charge CVCC (the VB regulator also powers the internal converter circuits as VVCC rises). Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 925 mA). Additionally, once the inrush period duration has also exceeded approximately 84 ms (end of inrush phase), the converter switching is allowed to start, once VVCC also goes above its UVLO (approximately 8.25 V).

Continuing the start-up sequence shown in Figure 8-9, once VVCC goes above its UVLO , the soft-start (SST) capacitor is first discharged with controlled current (ISSD) below nominally 0.2 V (VSFST) if the discharge was not already completed, then it is gradually recharged until it reaches ~0.25 V (VSSOFS in closed-loop mode) at which point the converter switching is enabled, following the closed loop controlled soft-start sequence. Note that the startup current source capability is such that it can fully maintain VVCC during the converter soft-start without requiring any significant CVCC capacitance, in 48 V input applications. At the end of the soft-start period, more specifically when SST voltage has exceeded ~2 V (VSTUOF), the startup current source is turned off. VVCC falls as it powers the internal circuits including the switching MOSFET gate. If the converter control-bias output rises to support VVCC before it falls to VCUVLO_F (~6.1 V), a successful start-up occurs. Figure 8-9 shows a small droop in VVCC while the output voltage rises smoothly and a successful start-up occurs.

Figure 8-10 also illustrates similar scenario if optocoupler feedback is used instead of PSR. In this case, the converter switching is enabled when VSST exceeds approximately 0.6 V (VSSOFS in peak current mode).

GUID-41AFA7EC-9E02-4C67-A4AB-12405871C68E-low.gif Figure 8-9 Power Up and Start - Flyback with PSR
GUID-542ECCC8-A542-44A0-AD1F-8CF38DE1707E-low.gifFigure 8-10 Power Up and Start - with Opto Feedback

The converter shuts off when VVCC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns off. A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is sometimes referred to as hiccup mode, which when combined with the soft-start provides robust output short protection by providing time-average heating reduction of the output rectifier.

Figure 8-11 illustrates the situation when there is severe overload at the main output which causes VCC hiccup. After VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start cycle is reinitiated, the soft-start capacitor being first discharged with controlled current, introducing a short pause before the output voltage is ramped up.

GUID-3D938F08-96E5-4A63-9100-EBEF120B73CE-low.gifFigure 8-11 Restart Following Severe Overload at Main Output of PSR Flyback DC-DC Converter

Also, when a VCC fall occurs, the TPS23731 can differentiate between an overload and a light load condition. For example a diode-rectified flyback with optocoupled feedback may have its VCC rail to fall in situation of light load due to temporary switching stop. In this case, the output voltage has to be maintained and a soft-start would not be acceptable. To address this case, if VVCC falls below approximately 7.1 V due to light load, the TPS23731 turns back on the startup immediately and for a short period of time to bring VCC voltage back up, and there is no soft-start recycling.

GUID-3DF6BCA0-F4E3-44DD-8A63-570449125868-low.gifFigure 8-12 Startup Operation if VCC Undervoltage is caused by Light Load Condition of Diode-rectified Flyback DC-DC Converter

If VVDD-VSS drops below the lower PoE UVLO (VUVLO_F, approximately 32 V), the hotswap MOSFET is turned off, but the converter still runs (unless LINEUV input is pulled low). The converter stops if VVCC falls below the VCUVLO_F (~6.1 V), the hotswap is in inrush current limit, the SST pin is pulled to ground, or the converter is in thermal shutdown.