JAJSN99A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 TVSP Device Configuration and ESD Protection

The Transient Voltage protection and firmware Setting Pin (TVSP) has three functions: 1) Boot configuration settings; 2) USB connector pin short to VBUS or VBAT protection; and 3) USB connector pin enhanced ESD protection.

  • RTVSP: At power on, the resistance between the TVSP pin and PGND determines the boot method, USB PD port I2C addresses and I2C logic thresholds. Refer to Table 9-4 and Table 9-5. The most common configuration is shown in Figure 9-4 with RTVSP open, corresponding to TVSP Index 0. During device initialization and boot, typically within 4 seconds after power on, VIN must be above 7.6 V to ensure proper bias of the TVSP pin to 5.5 V. Once boot is complete the device can operate over the full VIN range.
  • CTVSP: A 0.1-µF capacitor (CTVSP) must be connected to PGND. Place CTVSP as close to the TVSP pin as possible to minimize parasitic inductance. CTVSP is part of the centralized protection circuitry fortifying connector pins Px_CCy, Px_DP and Px_DM from damage during short to VBUS, VBAT and ESD events. A 40-V 0.1-µF capacitor is recommended for proper operation of the internal TVSP regulator circuit.
  • TVSP Damper Network: Capacitance, CDAMP, and resistance, RDAMP, form an RC network preventing excessive current from flowing inside the device durging connector pin over-voltage and ESD events.
    • CDAMP: A 0.47-µF capacitor must be connected in series with RDAMP to PGND. A 40-V 0.47-µF capacitor is recommended.
    • RDAMP: A 10-Ω resistor must be connected in series with CDAMP to PGND. A 0.25-W rating is recommended.

GUID-20201210-CA0I-5RN2-THXP-8VCDWVKS4ZXT-low.svg Figure 9-4 Basic TVSP Pin Connection
Table 9-3 Recommended TVSP Components
CTVSP RDAMP CDAMP
0.1 μF 10 Ω 0.47 μF
Table 9-4 RTVSP Configuration Settings (TPS25762CQRQLRQ1 and TPS25772CQRQLRQ1)
RTVSP (kΩ) (1) TVSP Index ADC Value I2C Target Port Addresses (A | B)(2) I2C Logic (VDD) Boot Mode
Open 0 ≤ 10 (0x0A) 0x22 | 0x26 3.3 V EEPROM
93.1 1 ≤ 24 (0x18) 0x23 | 0x27 3.3 V External HUB/MCU
47.5 2 ≤ 42 (0x2A) 0x22 | 0x26 1.8 V EEPROM
29.4 3 ≤ 63 (0x3F) 0x23 | 0x27 1.8 V External HUB/MCU
20.0 4 ≤ 89 (0x59) 0x23 | 0x27 3.3 V EEPROM
14.7 5 ≤ 119 (0x77) 0x22 | 0x26 3.3 V External HUB/MCU
11.0 6 ≤ 156 (0x9C) 0x23 | 0x27 1.8 V EEPROM
8.45 7 ≤ 201 (0xC9) 0x22 | 0x26 1.8 V External HUB/MCU
6.65 8 ≤ 255 (0xFF) 0x22 | 0x26 3.3 V Firmware Update
Table 9-5 RTVSP Configuration Settings (TPS25762CAQRQLRQ1 and TPS25762CAQRQLRQ1)
RTVSP (kΩ)(1) TVSP Index ADC Value I2C Target Port Addresses (A | B)(2) I2C Logic (VDD) Boot Mode
Open 0 ≤ 201 (0x0A) 0x22 | 0x26 3.3 V EEPROM
5.6 8 ≤ 255 (0xFF) 0x22 | 0x26 3.3 V Firmware Update
(1) 1% resistor required.
(2) 0x22h = 0100010; 0x26h = 0100110; 0x23h = 0100011; 0x27 = 0100111

Applications requiring a configuration other than standard, TVSP Index 0 (RTVSP open), as shown in Table 9-4 must implement a circuit similar to the one shown in Figure 9-5. The base of the bipolar transistor is connected to LDO_5V to provide proper power up sequencing of the TVSP resistor - OFF when TPS25772-Q1 is disabled and ON when TPS25772-Q1 is enabled. A 2N2222 is recommended for its large collector-emitter breakdown voltage, low-cost and wide availability.

GUID-20201210-CA0I-VKCH-CJPZ-L3DNXNCHW4RH-low.gif Figure 9-5 RTVSP Circuit Configuration

Device firmware can be updated using the USB Endpoint on the PA_DP and PA_DM pins. To enable firmware update mode, boot the device with a resistance corresponding to Index 8 between TVPS and PGND. A boot cycle can be performed by power cycling the device or by pulling the EN/UVLO pin momentarily below VEN(OPER) threshold. An example circuit to enable USB Endpoint firmware update mode is shown in Figure 9-6

GUID-20201210-CA0I-474L-SRKC-LVFPPSN3DT0F-low.gif Figure 9-6 Example Circuit to Enable USB Endpoint Firmware Update Mode