JAJSQE7A May   2023  – November 2023 TPS3808E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Voltage Thresholds
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
      2. 8.3.2 Selecting the RESET Delay Time
      3. 8.3.3 Manual RESET (MR) Input
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Modules
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Manual RESET (MR) Input

The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on MR causes RESET to assert. After MR returns to a logic high and SENSE is above the reset threshold, RESET is de-asserted after the user-defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ resistor, so this pin can be left unconnected if MR is not used.

See Figure 8-5 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR does not go fully to VDD, there is some additional current draw into VDD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 8-6.

GUID-20230414-SS0I-DRXW-CHR4-KNRKLDXVH6HM-low.svgFigure 8-5 Using MR to Monitor Multiple System Voltages
GUID-20230414-SS0I-T6W9-L7WJ-DM28GJR7HCSK-low.svgFigure 8-6 Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD