JAJSH97A April   2019  – September 2019 TPS3840-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 改訂履歴
  5. 概要(続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
        1. 9.3.1.1 VDD Hysteresis
        2. 9.3.1.2 VDD Transient Immunity
      2. 9.3.2 User-Programmable Reset Time Delay
      3. 9.3.3 Manual Reset (MR) Input
      4. 9.3.4 Output Logic
        1. 9.3.4.1 RESET Output, Active-Low
        2. 9.3.4.2 RESET Output, Active-High
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation (VDD > VDD(min))
      2. 9.4.2 VDD Between VPOR and VDD(min)
      3. 9.4.3 Below Power-On-Reset (VDD < VPOR)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Design 2: Automotive Off-Battery Monitoring
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves: TPS3840EVM
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイスの項目表記
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
TPS3840-Q1 IDDvsVDD_DL49.gifFigure 6. Supply Current vs Supply Voltage for TPS3840DL49-Q1
TPS3840-Q1 IDDvsVDD_PH49.gifFigure 8. Supply Current vs Supply Voltage for TPS3840PH49-Q1
TPS3840-Q1 VIT_accuracy_PL.gifFigure 10. Negative-going Input Threshold Accuracy over Temperature for TPS3840PL-Q1
TPS3840-Q1 Vhys_acc_vs_temp_DL.gifFigure 12. Input Threshold VIT- Hysteresis Accuracy for TPS3840DL-Q1
TPS3840-Q1 Vhys_acc_vs_temp_PH.gifFigure 14. Input Threshold VIT- Hysteresis Accuracy for TPS3840PH-Q1
TPS3840-Q1 VRESET_VDD_PL.gifFigure 16. Output Voltage vs Input Voltage for TPS3840PL49-Q1
TPS3840-Q1 VOL_IRESET_DL.gifFigure 18. Low Level Output Voltage vs IRESET for TPS3840DL49-Q1
TPS3840-Q1 VOL_IRESET_PL.gifFigure 20. Low Level Output Voltage vs IRESET for TPS3840PL49-Q1
TPS3840-Q1 VOL_IRESET_PH.gifFigure 22. Low Level Output Voltage vs IRESET for TPS3840PH49-Q1
TPS3840-Q1 VOH_IRESET_PL.gifFigure 24. High Level Output Voltage vs IRESET for TPS3840PL49-Q1
TPS3840-Q1 VOH_IRESET_PH.gifFigure 26. High Level Output Voltage vs IRESET for TPS3840PH49-Q1
TPS3840-Q1 MR_L_DL.gifFigure 28. Manual Reset Logic Low Voltage Threshold Over Temperature for TPS3840DL-Q1
TPS3840-Q1 MR_L_PH.gifFigure 30. Manual Reset Logic Low Voltage Threshold Over Temperature for TPS3840PH-Q1
TPS3840-Q1 MR_H_PL.gifFigure 32. Manual Reset Logic High Voltage Threshold Over Temperature for TPS3840PL-Q1
TPS3840-Q1 GlitchimmunityPL28.gifFigure 34. Glitch Immunity on VIT- vs Overdrive (Data Taken with TPS3840PL28-Q1)
TPS3840-Q1 Startuptime.gifFigure 36. Startup Delay Over Temperature
TPS3840-Q1 Delaywithcap.gifFigure 38. Reset Time Delay vs Capacitor Value (Data Taken with TPS3840PL16-Q1)
TPS3840-Q1 Delaywithcap_large.gifFigure 40. Reset Time Delay vs Large Capacitor Values (Data Taken with TPS3840PL16-Q1)
TPS3840-Q1 MR_res.gifFigure 42. Propagation Time Delay from MR Asserted to Reset Over Temperature
TPS3840-Q1 IDDvsVDD_PL49_smooth.gifFigure 7. Supply Current vs Supply Voltage for TPS3840PL49-Q1
TPS3840-Q1 VIT_accuracy_DL.gifFigure 9. Negative-going Input Threshold Accuracy over Temperature for TPS3840DL-Q1
TPS3840-Q1 VIT_accuracy_PH.gifFigure 11. Negative-going Input Threshold Accuracy over Temperature for TPS3840PH-Q1
TPS3840-Q1 Vhys_acc_vs_temp_PL.gifFigure 13. Input Threshold VIT- Hysteresis Accuracy for TPS3840PL-Q1
TPS3840-Q1 VRESET_VDD_DL.gifFigure 15. Output Voltage vs Input Voltage for TPS3840DL49-Q1
TPS3840-Q1 VRESET_VDD_PH.gifFigure 17. Output Voltage vs Input Voltage for TPS3840PH49-Q1
TPS3840-Q1 VOLvsVDD_DL49.gifFigure 19. Low Level Output Voltage vs VDD for TPS3840DL49-Q1
TPS3840-Q1 VOLvsVDD_PL49.gifFigure 21. Low Level Output Voltage vs VDD for TPS3840PL49-Q1
TPS3840-Q1 VOLvsVDD_PH49.gifFigure 23. Low Level Output Voltage vs VDD for TPS3840PH49-Q1
TPS3840-Q1 VOHvsVDD_PL49.gifFigure 25. High Level Output Voltage over Temperature for TPS3840PL49-Q1
TPS3840-Q1 VOHvsVDD_PH49.gifFigure 27. High Level Output Voltage Over Temperature for TPS3840PH49-Q1
TPS3840-Q1 MR_L_PL.gifFigure 29. Manual Reset Logic Low Voltage Threshold Over Temperature for TPS3840PL-Q1
TPS3840-Q1 MR_H_DL.gifFigure 31. Manual Reset Logic High Voltage Threshold Over Temperature for TPS3840DL-Q1
TPS3840-Q1 MR_H_PH.gifFigure 33. Manual Reset Logic High Voltage Threshold Over Temperature for TPS3840PH-Q1
TPS3840-Q1 RCTvsTemp.gifFigure 35. CT Pin Internal Resistance Over Temperature
TPS3840-Q1 DelayTimenocap.gifFigure 37. Reset Time Delay with No Capacitor Over Temperature
TPS3840-Q1 Delaywithcap_small.gifFigure 39. Reset Time Delay vs Small Capacitor Values (Data Taken with TPS3840PL16-Q1)
TPS3840-Q1 TPHL.gifFigure 41. Propagation Detect Time Delay for VDD Falling Below VIT- (High-to-Low) Over Temperature
TPS3840-Q1 MRdeassert.gifFigure 43. Propagation Time Delay from MR Release to Deasserted Reset Over Temperature