JAJSHK0B NOVEMBER   2008  – June 2019 TPS40197

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Package Dissipation Ratings
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable
      2. 8.3.2  Oscillator
      3. 8.3.3  UVLO
      4. 8.3.4  Start-up Sequence and Timing
      5. 8.3.5  Selecting the Short Circuit Current
      6. 8.3.6  Voltage Reference and Dynamic VID
      7. 8.3.7  Minimum On-Time Consideration
      8. 8.3.8  BP Regulator
      9. 8.3.9  Prebias Start-up
      10. 8.3.10 Drivers
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連デバイス
      2. 10.2.2 関連資料
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 コミュニティ・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGY Package
16-Pin VQFN
Top View
TPS40197 pinout_lus853.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 12 I Gate drive voltage for the high-side N-channel MOSFET. A 100-nF capacitor (typical) must be connected between this pin and SW.
BP 10 O Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 μF or greater from this pin to GND.
COMP 6 O Output of the error amplifier and connection node for loop feedback components.
EN 4 I Logic level input which starts or stops the controller from an external user command. A high level turns the controller on. A weak internal pullup holds this pin high so that the pin may be left floating if this function is not used. Pulling this pin low disables the controller.
FB 5 I Inverting input to the error amplifier.
HDRV 14 O Bootstrapped gate drive output for the high-side N-channel MOSFET.
LDRV 11 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET.
PGOOD 8 O Open drain power good output.
REF 3 I Non-Inverting input to the error amplifier. Its voltage range is from 0.9 V to 1.2 V in 20-mV steps. It is also internally connected to the DAC output through a unit gain buffer with 650-μA source/sink current capability. An external capacitor connected from this pin to GND programs the output voltage transition rate when VID code changes.
VDD 7 I Power input to the controller. Connect a 1-μF bypass capacitor closely from this pin to GND.
VID0 2 I Logic level inputs to the internal DAC that provides the reference voltage for output regulation. These pins are internally pulled up to a 1.68-V source with 80-μA pullup current.
VID1 1 I
VID2 16 I
VID3 15 I
GND 9 Ground connection to the controller