The TPS48100-Q1 feature adjustable short circuit protection. The threshold and response time can be adjusted using R_ISCP resistor and C_TMR capacitor respectively. The device senses the voltage across CS+ and CS– pins.

These pins can be connected across an external high and low side current sense resistor (R_SNS) or across the FET drain and source terminals for FET RDSON sensing as shown in Figure 7-5, Figure 7-6 and Figure 7-7 respectively.

Figure 7-5 TPS48100-Q1 Application Circuit With External Sense Resistor RSNS Based High Side Current Sensing

Figure 7-6 TPS48100-Q1 Application Circuit With External Sense Resistor RSNS Based Low Side Current Sensing

Figure 7-7 TPS48100-Q1 Application Circuit with MOSFET RDSON Based Current Sensing

Set the short-circuit detection threshold using an external R_ISCP resistor across ISCP and GND pins. Use Equation 5 to calculate the required R_ISCP value:

Refer to Equation 9 in Application Limitations section for update in equation in final revision of IC.

Where,

R_SNS is the current sense resistor value or the FET R_DSON value.

I_SC is the desired short circuit current level.

The short circuit protection response is fastest with no C_TMR cap connected across TMR and GND pins.

With device powered ON and EN/UVLO, INP pulled high, During Q1 turn ON, first VGS of external FET Q1 (G1 gate drive) is sensed by monitoring the voltage across G1PD to SRC. Once G1PD to SRC voltage raises above V_{(G1_GOOD)} threshold which ensures that the external FET is enhanced, then the SCP comparator output is monitored. If the sensed voltage across CS+ and CS– exceeds the short-circuit set point (V_SCP), G1PD pulls low to SRC and FLT asserts. Subsequent events can be set either to be auto-retry or latch off as described in following sections.

VGS of external FET (Q1) is only monitored when CS_SEL is pulled low. VGS of external FET (Q1) is not monitored for low side current sensing as shown in Figure 7-6.