JAJSEU4D December   2015  – December 2019 TPS4H160-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
      2.      可変電流制限による容量性負荷の駆動
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Pin Current and Voltage Conventions
      2. 9.3.2 Accurate Current Sense
      3. 9.3.3 Adjustable Current Limit
      4. 9.3.4 Inductive-Load Switching-Off Clamp
      5. 9.3.5 Fault Detection and Reporting
        1. 9.3.5.1 Diagnostic Enable Function
        2. 9.3.5.2 Multiplexing of Current Sense
        3. 9.3.5.3 Fault Table
        4. 9.3.5.4 STx and FAULT Reporting
      6. 9.3.6 Full Diagnostics
        1. 9.3.6.1 Short-to-GND and Overload Detection
        2. 9.3.6.2 Open-Load Detection
          1. 9.3.6.2.1 Channel On
          2. 9.3.6.2.2 Channel Off
        3. 9.3.6.3 Short-to-Battery Detection
        4. 9.3.6.4 Reverse Polarity Detection
        5. 9.3.6.5 Thermal Fault Detection
          1. 9.3.6.5.1 Thermal Shutdown
      7. 9.3.7 Full Protections
        1. 9.3.7.1 UVLO Protection
        2. 9.3.7.2 Loss-of-GND Protection
        3. 9.3.7.3 Protection for Loss of Power Supply
        4. 9.3.7.4 Reverse-Current Protection
        5. 9.3.7.5 MCU I/O Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Working Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 Without a GND Network
      2. 12.2.2 With a GND Network
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.4 Inductive-Load Switching-Off Clamp

When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp between drain and source is implemented, namely VDS(clamp).

Equation 5. TPS4H160-Q1 eq05-Vds-clamp_SLVSCV8.gif

During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The total energy is dissipated in the high-side switch. Total energy includes the energy of the power supply (E(VS)) and the energy of the load (E(load)). If resistance is in series with inductance, some of the load energy is dissipated on the resistance.

Equation 6. TPS4H160-Q1 eq06-Ehss_SLVSCV8.gif

When an inductive load switches off, E(HSS) causes high thermal stressing on the device.. The upper limit of the power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.

TPS4H160-Q1 D-to-S-clamp_SLVSCV8.gifFigure 24. Drain-to-Source Clamping Structure
TPS4H160-Q1 load-switching_SLVSCV8.gifFigure 25. Inductive Load Switching-Off Diagram

From the perspective of the high-side switch, E(HSS) equals the integration value during the demagnetization period.

Equation 7. TPS4H160-Q1 eq07-Ehss_SLVSCV8.gif

When R approximately equals 0, E(HSD) can be given simply as:

Equation 8. TPS4H160-Q1 eq08-Ehss2_SLVSCV8.gif

Figure 26 is a waveform of the device driving an inductive load, and Figure 27 is waveform with an expanded time scale. Channel 1 is the IN signal, channel 2 is the supply voltage VVS, channel 3 is the output voltage VOUT, channel 4 is the output current IOUT, and channel M is the measured power dissipation E(HSS).

On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device also optimizes the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the effects of transient power and EMI to a minimum. As shown in Figure 26 and Figure 27, the controlled slew rate is around 0.5 V/µs.

TPS4H160-Q1 load-sw-off_SLVSCV8.gifFigure 26. Inductive Load Switching-Off Waveform
TPS4H160-Q1 load-sw-off2_SLVSCV8.gifFigure 27. Inductive Load Switching-Off Expanded Waveform

Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown in Figure 28 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See Figure 28 for more details.

TPS4H160-Q1 prot_ext-circ_SLVSCV8.gifFigure 28. Protection With External Circuitry