JAJSH63C JULY   2012  – April 2019 TPS53015

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Drivers
      2. 7.3.2 5-Volt Regulator
      3. 7.3.3 Soft-Start and Pre-biased Soft-Start Time
      4. 7.3.4 Overcurrent Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
      8. 7.3.8 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 Auto-skip Eco-Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine the Inductance Value
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Bootstrap Capacitor
        5. 8.2.2.5 VREG5 Capacitor
        6. 8.2.2.6 Choose Output Voltage Resistors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 商標
    2. 11.2 静電気放電に関する注意事項
    3. 11.3 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
TPS53015 pinout_slusck2.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
DRVH 9 O High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and VBST(ON).
DRVL 7 O Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF) and VREG5(ON).
EN 4 I Enable. Pull high to enable converter.
PG 2 O Open drain power good output.
PGND 6 I System ground.
SW 8 I/O Switch node connections for both the high-side driver and overcurrent comparator.
VBST 10 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal diode is connected between VREG5 and VBST
VFB 1 I D-CAP2 feedback input. Connect to output voltage with resistor divider.
VIN 5 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-μF high quality ceramic capacitor.
VREG5 3 O Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-μF high-quality ceramic capacitor. VREG5 is active when EN is asserted high.
(1) I = input, O = output