JAJS448D March   2010  – October 2018 TPS54260

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Pulse-Skip Eco-Mode
      4. 8.3.4  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Voltage Reference
      7. 8.3.7  Adjusting the Output Voltage
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Slow-Start / Tracking Pin (SS/TR)
      10. 8.3.10 Overload Recovery Circuit
      11. 8.3.11 Sequencing
      12. 8.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 8.3.13 Overcurrent Protection and Frequency Shift
      14. 8.3.14 Selecting the Switching Frequency
      15. 8.3.15 How to Interface to RT/CLK Pin
      16. 8.3.16 Powergood (PWRGD Pin)
      17. 8.3.17 Overvoltage Transient Protection
      18. 8.3.18 Thermal Shutdown
      19. 8.3.19 Small Signal Model for Loop Response
      20. 8.3.20 Simple Small Signal Model for Peak Current Mode Control
      21. 8.3.21 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation Near Minimum Input Voltage
      2. 8.4.2 Operation With Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V Output Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Selecting the Switching Frequency
          3. 9.2.1.2.3  Output Inductor Selection (LO)
          4. 9.2.1.2.4  Output Capacitor
          5. 9.2.1.2.5  Catch Diode
          6. 9.2.1.2.6  Input Capacitor
          7. 9.2.1.2.7  Slow-Start Capacitor
          8. 9.2.1.2.8  Bootstrap Capacitor Selection
          9. 9.2.1.2.9  Undervoltage Lock Out Set Point
          10. 9.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 9.2.1.2.11 Compensation
          12. 9.2.1.2.12 Discontinuous Mode and Eco-Mode Boundary
          13. 9.2.1.2.13 Power Dissipation Estimate
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inverting Power Supply
      3. 9.2.3 Split-Rail Power Supply
      4. 9.2.4 12-V to 3.8-V GSM Power Supply
      5. 9.2.5 24-V to 4.2-V GSM Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.14 Selecting the Switching Frequency

The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.

Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the fsw(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 V, the fdiv integer increases from 1 to 8 corresponding to the frequency shift.

In Figure 41, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is 0 V, and the resistance of the inductor is 0.130 Ω, FET on resistance of 0.2 Ω and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching frequency.

Equation 12. TPS54260 q_fswmaxskip_lvs795.gif
Equation 13. TPS54260 q_fswmaxshift_lvsa86.gif

where

  • IL = inductor current
  • Rdc = inductor resistance
  • VIN = maximum input voltage
  • VOUT = output voltage
  • VOUTSC =output voltage during short
  • Vd = diode voltage drop
  • RDS(on) = switch on resistance
  • tON = controllable on time
  • ƒDIV = frequency divide equals (1, 2, 4, or 8)
TPS54260 C027_SLVS919.gifFigure 41. Maximum Switching Frequency vs Input Voltage