JAJSOP7A June   2011  – July 2022 TPS54325-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start and Pre-Biased Soft Start
      2. 7.3.2 Power Good
      3. 7.3.3 Output Discharge Control
      4. 7.3.4 Current Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 PWM Frequency and Adaptive On-Time Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
        6. 8.2.2.6 VREG5 Capacitor Selection
        7. 8.2.2.7 Output Voltage Resistors Selection
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-3A4B2F4A-BB17-43C5-B4DD-F79553FBBAAA-low.gif Figure 5-1 14-Pin PWP HTSSOP Pinout
Table 5-1 Pin Functions
Pin Description
Name NO.
VO 1 Connect this pin to the output of the converter. This pin is used for on-time adjustment.
VFB 2 Converter feedback input. Connect this pin with a feedback resistor divider.
VREG5 3 5.5-V power supply output. Connect a capacitor (typically 1μF) to GND.
SS 4 Soft-start control. Connect an external capacitor to GND.
GND 5 Signal ground pin
PG 6 Open-drain power-good output
EN 7 Enable control input
PGND1, PGND2 8, 9 Ground returns for low-side MOSFET. These ground returns also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC.
SW1, SW2 10, 11 Switch node connections between the high-side NFET and low-side NFET. These connections also serve as inputs to current comparators.
VBST 12 Supply input for high-side NFET gate driver (boost terminal). Connect a capacitor from this pin to respective SW1 and SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
VIN 13 Power input and connected to high-side NFET drain
VCC 14 Supply input for the 5-V internal linear regulator for the control circuitry
PowerPAD Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Connect to GND.