SLVSBZ0A September   2013  – December 2014 TPS54560-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-Mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLK Pin
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI = 4.5 V (Minimum VDD)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Alternative Power-Supply Topologies
        1. 7.4.3.1 Inverting Power Supply
        2. 7.4.3.2 Split-Rail Power Supply
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Bootstrap Capacitor Selection
        7. 8.2.2.7  Undervoltage Lockout Set Point
        8. 8.2.2.8  Output Voltage and Feedback Resistors Selection
        9. 8.2.2.9  Compensation
        10. 8.2.2.10 Discontinuous Conduction Mode and Eco-Mode Boundary
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Safe Operating Area
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the A node of the catch diode. See Figure 57 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

new-layout_lvsbb4-3.gifFigure 57. PCB Layout Example

10.3 Power Dissipation

The following formulas show how to estimate the TPS54560-Q1 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.

Equation 50. q_50_lvsBN0.gif

Equation 51. q_51_lvsBN0.gif

Equation 52. q_52_lvsBN0.gif

Equation 53. q_pq_lvsb44.gif

Where:

IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current

Therefore,

Equation 54. q_54_lvsBN0.gif

For given TA,

Equation 55. q_tj_lvs795.gif

For given TJMAX = 150°C

Equation 56. q_tamax_lvs795.gif

Where:

Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).

There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator.

10.4 Safe Operating Area

The safe operating area (SOA) of the device is shown in Figure 58, through Figure 61 for 3.3 V, 5 V and 12 V outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at which the internal components are at or below the manufacturer’s maximum operating temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar to the EVM. Careful attention must be paid to the other components chosen for the design, especially the catch diode.

C047_SLVSBZ0.pngFigure 58. 3.3-V Outputs
C049_SLVSBZ0.pngFigure 60. 12-V Outputs
C048_SLVSBZ0.pngFigure 59. 5-V Outputs
C050_SLVSBZ0.pngFigure 61. Air Flow Conditions
VIN = 36 V, VO = 12 V