The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 7-7. In Type 2A, one additional high-frequency pole, C6, is added to attenuate high frequency noise. In Type III, one additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III Compensation for Current Mode Step-Down Converters for a complete explanation of Type III compensation.

The design guidelines below are provided for advanced users who prefer to compensate using the general method. The following equations only apply to designs whose ESR zero is above the bandwidth of the control loop. This is usually true with ceramic output capacitors. See Application and Implementation for a step-by-step design procedure using higher ESR output capacitors with lower ESR zero frequencies.

Figure 7-7 Types of Frequency Compensation

The general design guidelines for device loop compensation are as follows:

1. Determine the crossover frequency, fc. A good starting point is 1/10^th of the switching frequency, fsw.
2. R4 can be determined by:
   Equation 9.

   where

   • gm_ea is the GM amplifier gain (1300 μA/V).
   • gm_ps is the power stage gain (16 A/V).
   • Vref is the reference voltage (0.6 V).
3. Place a compensation zero at the dominant pole:
   C4 can be determined by:
   Equation 10.
4. C6 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output capacitor C_O.
   Equation 11.
5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 12.
   Equation 12.